You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
135 lines
5.4 KiB
135 lines
5.4 KiB
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
|
# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
|
|
|
|
--- |
|
|
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
|
|
target triple = "thumbv8.1m.main"
|
|
|
|
define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
|
|
entry:
|
|
%scevgep = getelementptr i32, i32* %q, i32 -1
|
|
%scevgep3 = getelementptr i32, i32* %p, i32 -1
|
|
%start = call i32 @llvm.start.loop.iterations.i32(i32 %n)
|
|
br label %while.body
|
|
|
|
while.body: ; preds = %while.body, %entry
|
|
%lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ]
|
|
%lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ]
|
|
%0 = phi i32 [ %start, %entry ], [ %2, %while.body ]
|
|
%scevgep6 = getelementptr i32, i32* %lsr.iv, i32 1
|
|
%scevgep2 = getelementptr i32, i32* %lsr.iv4, i32 1
|
|
%1 = load i32, i32* %scevgep6, align 4
|
|
store i32 %1, i32* %scevgep2, align 4
|
|
%scevgep1 = getelementptr i32, i32* %lsr.iv, i32 1
|
|
%scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
|
|
%2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
|
|
%3 = icmp ne i32 %2, 0
|
|
br i1 %3, label %while.body, label %while.end
|
|
|
|
while.end: ; preds = %while.body
|
|
ret i32 0
|
|
}
|
|
|
|
declare i32 @llvm.start.loop.iterations.i32(i32) #0
|
|
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
|
|
|
|
attributes #0 = { noduplicate nounwind }
|
|
attributes #1 = { nounwind }
|
|
|
|
...
|
|
---
|
|
name: do_copy
|
|
alignment: 2
|
|
exposesReturnsTwice: false
|
|
legalized: false
|
|
regBankSelected: false
|
|
selected: false
|
|
failedISel: false
|
|
tracksRegLiveness: true
|
|
hasWinCFI: false
|
|
registers: []
|
|
liveins:
|
|
- { reg: '$r0', virtual-reg: '' }
|
|
- { reg: '$r1', virtual-reg: '' }
|
|
- { reg: '$r2', virtual-reg: '' }
|
|
frameInfo:
|
|
isFrameAddressTaken: false
|
|
isReturnAddressTaken: false
|
|
hasStackMap: false
|
|
hasPatchPoint: false
|
|
stackSize: 8
|
|
offsetAdjustment: 0
|
|
maxAlignment: 4
|
|
adjustsStack: false
|
|
hasCalls: false
|
|
stackProtector: ''
|
|
maxCallFrameSize: 0
|
|
cvBytesOfCalleeSavedRegisters: 0
|
|
hasOpaqueSPAdjustment: false
|
|
hasVAStart: false
|
|
hasMustTailInVarArgFunc: false
|
|
localFrameSize: 0
|
|
savePoint: ''
|
|
restorePoint: ''
|
|
fixedStack: []
|
|
stack:
|
|
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
|
|
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
|
|
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
|
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
|
|
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
|
|
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
|
callSites: []
|
|
constants: []
|
|
machineFunctionInfo: {}
|
|
body: |
|
|
; CHECK-LABEL: name: do_copy
|
|
; CHECK: bb.0.entry:
|
|
; CHECK: successors: %bb.1(0x80000000)
|
|
; CHECK: liveins: $lr, $r0, $r1, $r2, $r7
|
|
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
|
|
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
|
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
|
|
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
|
|
; CHECK: dead $lr = t2DLS $r0
|
|
; CHECK: $lr = tMOVr killed $r0, 14 /* CC::al */, $noreg
|
|
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14 /* CC::al */, $noreg
|
|
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14 /* CC::al */, $noreg
|
|
; CHECK: bb.1.while.body:
|
|
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
|
|
; CHECK: liveins: $lr, $r0, $r1
|
|
; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load 4 from %ir.scevgep6)
|
|
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14 /* CC::al */, $noreg :: (store 4 into %ir.scevgep2)
|
|
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
|
|
; CHECK: bb.2.while.end:
|
|
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
|
|
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
|
|
bb.0.entry:
|
|
successors: %bb.1(0x80000000)
|
|
liveins: $r0, $r1, $r2, $r7, $lr
|
|
|
|
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
|
|
frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
|
frame-setup CFI_INSTRUCTION offset $lr, -4
|
|
frame-setup CFI_INSTRUCTION offset $r7, -8
|
|
$lr = t2DoLoopStart $r0
|
|
$lr = tMOVr killed $r0, 14, $noreg
|
|
renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
|
|
renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
|
|
|
|
bb.1.while.body:
|
|
successors: %bb.1(0x7c000000), %bb.2(0x04000000)
|
|
liveins: $lr, $r0, $r1
|
|
|
|
renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)
|
|
early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)
|
|
renamable $lr = t2LoopDec killed renamable $lr, 1
|
|
t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
|
|
tB %bb.2, 14, $noreg
|
|
|
|
bb.2.while.end:
|
|
$r0, dead $cpsr = tMOVi8 0, 14, $noreg
|
|
tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
|
|
|
|
...
|