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2050 lines
73 KiB
2050 lines
73 KiB
//===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Pass to verify generated machine code. The following is checked:
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//
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// Operand counts: All explicit operands must be present.
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//
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// Register classes: All physical and virtual register operands must be
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// compatible with the register class required by the instruction descriptor.
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//
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// Register live intervals: Registers must be defined only once, and must be
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// defined before use.
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//
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// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
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// command-line option -verify-machineinstrs, or by defining the environment
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// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
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// the verifier errors.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SetOperations.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Analysis/EHPersonalities.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FileSystem.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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namespace {
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struct MachineVerifier {
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MachineVerifier(Pass *pass, const char *b) :
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PASS(pass),
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Banner(b)
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{}
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unsigned verify(MachineFunction &MF);
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Pass *const PASS;
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const char *Banner;
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const MachineFunction *MF;
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const MachineRegisterInfo *MRI;
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unsigned foundErrors;
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typedef SmallVector<unsigned, 16> RegVector;
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typedef SmallVector<const uint32_t*, 4> RegMaskVector;
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typedef DenseSet<unsigned> RegSet;
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typedef DenseMap<unsigned, const MachineInstr*> RegMap;
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typedef SmallPtrSet<const MachineBasicBlock*, 8> BlockSet;
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const MachineInstr *FirstTerminator;
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BlockSet FunctionBlocks;
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BitVector regsReserved;
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RegSet regsLive;
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RegVector regsDefined, regsDead, regsKilled;
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RegMaskVector regMasks;
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RegSet regsLiveInButUnused;
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SlotIndex lastIndex;
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// Add Reg and any sub-registers to RV
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void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
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RV.push_back(Reg);
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
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RV.push_back(*SubRegs);
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}
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struct BBInfo {
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// Is this MBB reachable from the MF entry point?
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bool reachable;
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// Vregs that must be live in because they are used without being
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// defined. Map value is the user.
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RegMap vregsLiveIn;
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// Regs killed in MBB. They may be defined again, and will then be in both
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// regsKilled and regsLiveOut.
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RegSet regsKilled;
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// Regs defined in MBB and live out. Note that vregs passing through may
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// be live out without being mentioned here.
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RegSet regsLiveOut;
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// Vregs that pass through MBB untouched. This set is disjoint from
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// regsKilled and regsLiveOut.
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RegSet vregsPassed;
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// Vregs that must pass through MBB because they are needed by a successor
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// block. This set is disjoint from regsLiveOut.
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RegSet vregsRequired;
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// Set versions of block's predecessor and successor lists.
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BlockSet Preds, Succs;
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BBInfo() : reachable(false) {}
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// Add register to vregsPassed if it belongs there. Return true if
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// anything changed.
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bool addPassed(unsigned Reg) {
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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return false;
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if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
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return false;
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return vregsPassed.insert(Reg).second;
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}
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// Same for a full set.
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bool addPassed(const RegSet &RS) {
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bool changed = false;
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for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
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if (addPassed(*I))
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changed = true;
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return changed;
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}
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// Add register to vregsRequired if it belongs there. Return true if
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// anything changed.
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bool addRequired(unsigned Reg) {
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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return false;
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if (regsLiveOut.count(Reg))
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return false;
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return vregsRequired.insert(Reg).second;
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}
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// Same for a full set.
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bool addRequired(const RegSet &RS) {
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bool changed = false;
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for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
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if (addRequired(*I))
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changed = true;
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return changed;
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}
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// Same for a full map.
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bool addRequired(const RegMap &RM) {
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bool changed = false;
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for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
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if (addRequired(I->first))
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changed = true;
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return changed;
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}
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// Live-out registers are either in regsLiveOut or vregsPassed.
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bool isLiveOut(unsigned Reg) const {
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return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
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}
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};
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// Extra register info per MBB.
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DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
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bool isReserved(unsigned Reg) {
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return Reg < regsReserved.size() && regsReserved.test(Reg);
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}
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bool isAllocatable(unsigned Reg) {
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return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
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}
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// Analysis information if available
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LiveVariables *LiveVars;
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LiveIntervals *LiveInts;
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LiveStacks *LiveStks;
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SlotIndexes *Indexes;
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void visitMachineFunctionBefore();
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void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
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void visitMachineBundleBefore(const MachineInstr *MI);
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void visitMachineInstrBefore(const MachineInstr *MI);
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void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
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void visitMachineInstrAfter(const MachineInstr *MI);
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void visitMachineBundleAfter(const MachineInstr *MI);
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void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
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void visitMachineFunctionAfter();
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template <typename T> void report(const char *msg, ilist_iterator<T> I) {
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report(msg, &*I);
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}
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void report(const char *msg, const MachineFunction *MF);
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void report(const char *msg, const MachineBasicBlock *MBB);
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void report(const char *msg, const MachineInstr *MI);
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void report(const char *msg, const MachineOperand *MO, unsigned MONum);
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void report_context(const LiveInterval &LI) const;
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void report_context(const LiveRange &LR, unsigned Reg,
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LaneBitmask LaneMask) const;
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void report_context(const LiveRange::Segment &S) const;
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void report_context(const VNInfo &VNI) const;
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void report_context(SlotIndex Pos) const;
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void report_context_liverange(const LiveRange &LR) const;
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void report_context_lanemask(LaneBitmask LaneMask) const;
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void report_context_vreg(unsigned VReg) const;
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void report_context_vreg_regunit(unsigned VRegOrRegUnit) const;
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void verifyInlineAsm(const MachineInstr *MI);
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void checkLiveness(const MachineOperand *MO, unsigned MONum);
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void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
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SlotIndex UseIdx, const LiveRange &LR, unsigned Reg,
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LaneBitmask LaneMask = 0);
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void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
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SlotIndex DefIdx, const LiveRange &LR, unsigned Reg,
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LaneBitmask LaneMask = 0);
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void markReachable(const MachineBasicBlock *MBB);
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void calcRegsPassed();
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void checkPHIOps(const MachineBasicBlock *MBB);
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void calcRegsRequired();
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void verifyLiveVariables();
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void verifyLiveIntervals();
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void verifyLiveInterval(const LiveInterval&);
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void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned,
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unsigned);
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void verifyLiveRangeSegment(const LiveRange&,
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const LiveRange::const_iterator I, unsigned,
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unsigned);
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void verifyLiveRange(const LiveRange&, unsigned, LaneBitmask LaneMask = 0);
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void verifyStackFrame();
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void verifySlotIndexes() const;
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void verifyProperties(const MachineFunction &MF);
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};
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struct MachineVerifierPass : public MachineFunctionPass {
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static char ID; // Pass ID, replacement for typeid
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const std::string Banner;
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MachineVerifierPass(const std::string &banner = nullptr)
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: MachineFunctionPass(ID), Banner(banner) {
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initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
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if (FoundErrors)
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report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
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return false;
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}
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};
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}
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char MachineVerifierPass::ID = 0;
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INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
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"Verify generated machine code", false, false)
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FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
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return new MachineVerifierPass(Banner);
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}
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bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
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const {
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MachineFunction &MF = const_cast<MachineFunction&>(*this);
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unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
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if (AbortOnErrors && FoundErrors)
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report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
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return FoundErrors == 0;
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}
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void MachineVerifier::verifySlotIndexes() const {
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if (Indexes == nullptr)
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return;
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// Ensure the IdxMBB list is sorted by slot indexes.
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SlotIndex Last;
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for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
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E = Indexes->MBBIndexEnd(); I != E; ++I) {
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assert(!Last.isValid() || I->first > Last);
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Last = I->first;
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}
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}
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void MachineVerifier::verifyProperties(const MachineFunction &MF) {
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// If a pass has introduced virtual registers without clearing the
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// AllVRegsAllocated property (or set it without allocating the vregs)
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// then report an error.
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::AllVRegsAllocated) &&
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MRI->getNumVirtRegs()) {
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report(
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"Function has AllVRegsAllocated property but there are VReg operands",
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&MF);
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}
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}
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unsigned MachineVerifier::verify(MachineFunction &MF) {
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foundErrors = 0;
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this->MF = &MF;
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TM = &MF.getTarget();
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TII = MF.getSubtarget().getInstrInfo();
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TRI = MF.getSubtarget().getRegisterInfo();
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MRI = &MF.getRegInfo();
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LiveVars = nullptr;
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LiveInts = nullptr;
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LiveStks = nullptr;
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Indexes = nullptr;
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if (PASS) {
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LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
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// We don't want to verify LiveVariables if LiveIntervals is available.
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if (!LiveInts)
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LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
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LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
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Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
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}
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verifySlotIndexes();
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verifyProperties(MF);
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visitMachineFunctionBefore();
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for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
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MFI!=MFE; ++MFI) {
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visitMachineBasicBlockBefore(&*MFI);
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// Keep track of the current bundle header.
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const MachineInstr *CurBundle = nullptr;
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// Do we expect the next instruction to be part of the same bundle?
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bool InBundle = false;
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for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
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MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
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if (MBBI->getParent() != &*MFI) {
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report("Bad instruction parent pointer", MFI);
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errs() << "Instruction: " << *MBBI;
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continue;
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}
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// Check for consistent bundle flags.
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if (InBundle && !MBBI->isBundledWithPred())
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report("Missing BundledPred flag, "
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"BundledSucc was set on predecessor",
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&*MBBI);
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if (!InBundle && MBBI->isBundledWithPred())
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report("BundledPred flag is set, "
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"but BundledSucc not set on predecessor",
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&*MBBI);
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// Is this a bundle header?
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if (!MBBI->isInsideBundle()) {
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if (CurBundle)
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visitMachineBundleAfter(CurBundle);
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CurBundle = &*MBBI;
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visitMachineBundleBefore(CurBundle);
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} else if (!CurBundle)
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report("No bundle header", MBBI);
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visitMachineInstrBefore(&*MBBI);
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for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
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const MachineInstr &MI = *MBBI;
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const MachineOperand &Op = MI.getOperand(I);
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if (Op.getParent() != &MI) {
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// Make sure to use correct addOperand / RemoveOperand / ChangeTo
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// functions when replacing operands of a MachineInstr.
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report("Instruction has operand with wrong parent set", &MI);
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}
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visitMachineOperand(&Op, I);
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}
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visitMachineInstrAfter(&*MBBI);
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// Was this the last bundled instruction?
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InBundle = MBBI->isBundledWithSucc();
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}
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if (CurBundle)
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visitMachineBundleAfter(CurBundle);
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if (InBundle)
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report("BundledSucc flag set on last instruction in block", &MFI->back());
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visitMachineBasicBlockAfter(&*MFI);
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}
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visitMachineFunctionAfter();
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// Clean up.
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regsLive.clear();
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regsDefined.clear();
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regsDead.clear();
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regsKilled.clear();
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regMasks.clear();
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regsLiveInButUnused.clear();
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MBBInfoMap.clear();
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return foundErrors;
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}
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void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
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assert(MF);
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errs() << '\n';
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if (!foundErrors++) {
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if (Banner)
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errs() << "# " << Banner << '\n';
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if (LiveInts != nullptr)
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LiveInts->print(errs());
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else
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MF->print(errs(), Indexes);
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}
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errs() << "*** Bad machine code: " << msg << " ***\n"
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<< "- function: " << MF->getName() << "\n";
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}
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void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
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assert(MBB);
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report(msg, MBB->getParent());
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errs() << "- basic block: BB#" << MBB->getNumber()
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<< ' ' << MBB->getName()
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<< " (" << (const void*)MBB << ')';
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if (Indexes)
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errs() << " [" << Indexes->getMBBStartIdx(MBB)
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<< ';' << Indexes->getMBBEndIdx(MBB) << ')';
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errs() << '\n';
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}
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void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
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assert(MI);
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report(msg, MI->getParent());
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errs() << "- instruction: ";
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if (Indexes && Indexes->hasIndex(*MI))
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errs() << Indexes->getInstructionIndex(*MI) << '\t';
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MI->print(errs(), /*SkipOpers=*/true);
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errs() << '\n';
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}
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void MachineVerifier::report(const char *msg,
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const MachineOperand *MO, unsigned MONum) {
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assert(MO);
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report(msg, MO->getParent());
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errs() << "- operand " << MONum << ": ";
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MO->print(errs(), TRI);
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errs() << "\n";
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}
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void MachineVerifier::report_context(SlotIndex Pos) const {
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errs() << "- at: " << Pos << '\n';
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}
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void MachineVerifier::report_context(const LiveInterval &LI) const {
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errs() << "- interval: " << LI << '\n';
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}
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void MachineVerifier::report_context(const LiveRange &LR, unsigned Reg,
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LaneBitmask LaneMask) const {
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report_context_liverange(LR);
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errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
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if (LaneMask != 0)
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report_context_lanemask(LaneMask);
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}
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void MachineVerifier::report_context(const LiveRange::Segment &S) const {
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errs() << "- segment: " << S << '\n';
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}
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void MachineVerifier::report_context(const VNInfo &VNI) const {
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errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
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}
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void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
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errs() << "- liverange: " << LR << '\n';
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}
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void MachineVerifier::report_context_vreg(unsigned VReg) const {
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errs() << "- v. register: " << PrintReg(VReg, TRI) << '\n';
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}
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void MachineVerifier::report_context_vreg_regunit(unsigned VRegOrUnit) const {
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if (TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
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|
report_context_vreg(VRegOrUnit);
|
|
} else {
|
|
errs() << "- regunit: " << PrintRegUnit(VRegOrUnit, TRI) << '\n';
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
|
|
errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
|
|
}
|
|
|
|
void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
|
|
BBInfo &MInfo = MBBInfoMap[MBB];
|
|
if (!MInfo.reachable) {
|
|
MInfo.reachable = true;
|
|
for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
|
|
SuE = MBB->succ_end(); SuI != SuE; ++SuI)
|
|
markReachable(*SuI);
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::visitMachineFunctionBefore() {
|
|
lastIndex = SlotIndex();
|
|
regsReserved = MRI->getReservedRegs();
|
|
|
|
// A sub-register of a reserved register is also reserved
|
|
for (int Reg = regsReserved.find_first(); Reg>=0;
|
|
Reg = regsReserved.find_next(Reg)) {
|
|
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
|
|
// FIXME: This should probably be:
|
|
// assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
|
|
regsReserved.set(*SubRegs);
|
|
}
|
|
}
|
|
|
|
markReachable(&MF->front());
|
|
|
|
// Build a set of the basic blocks in the function.
|
|
FunctionBlocks.clear();
|
|
for (const auto &MBB : *MF) {
|
|
FunctionBlocks.insert(&MBB);
|
|
BBInfo &MInfo = MBBInfoMap[&MBB];
|
|
|
|
MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
|
|
if (MInfo.Preds.size() != MBB.pred_size())
|
|
report("MBB has duplicate entries in its predecessor list.", &MBB);
|
|
|
|
MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
|
|
if (MInfo.Succs.size() != MBB.succ_size())
|
|
report("MBB has duplicate entries in its successor list.", &MBB);
|
|
}
|
|
|
|
// Check that the register use lists are sane.
|
|
MRI->verifyUseLists();
|
|
|
|
verifyStackFrame();
|
|
}
|
|
|
|
// Does iterator point to a and b as the first two elements?
|
|
static bool matchPair(MachineBasicBlock::const_succ_iterator i,
|
|
const MachineBasicBlock *a, const MachineBasicBlock *b) {
|
|
if (*i == a)
|
|
return *++i == b;
|
|
if (*i == b)
|
|
return *++i == a;
|
|
return false;
|
|
}
|
|
|
|
void
|
|
MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
|
|
FirstTerminator = nullptr;
|
|
|
|
if (MRI->isSSA()) {
|
|
// If this block has allocatable physical registers live-in, check that
|
|
// it is an entry block or landing pad.
|
|
for (const auto &LI : MBB->liveins()) {
|
|
if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
|
|
MBB->getIterator() != MBB->getParent()->begin()) {
|
|
report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Count the number of landing pad successors.
|
|
SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
|
|
for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
|
|
E = MBB->succ_end(); I != E; ++I) {
|
|
if ((*I)->isEHPad())
|
|
LandingPadSuccs.insert(*I);
|
|
if (!FunctionBlocks.count(*I))
|
|
report("MBB has successor that isn't part of the function.", MBB);
|
|
if (!MBBInfoMap[*I].Preds.count(MBB)) {
|
|
report("Inconsistent CFG", MBB);
|
|
errs() << "MBB is not in the predecessor list of the successor BB#"
|
|
<< (*I)->getNumber() << ".\n";
|
|
}
|
|
}
|
|
|
|
// Check the predecessor list.
|
|
for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
|
|
E = MBB->pred_end(); I != E; ++I) {
|
|
if (!FunctionBlocks.count(*I))
|
|
report("MBB has predecessor that isn't part of the function.", MBB);
|
|
if (!MBBInfoMap[*I].Succs.count(MBB)) {
|
|
report("Inconsistent CFG", MBB);
|
|
errs() << "MBB is not in the successor list of the predecessor BB#"
|
|
<< (*I)->getNumber() << ".\n";
|
|
}
|
|
}
|
|
|
|
const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
|
|
const BasicBlock *BB = MBB->getBasicBlock();
|
|
const Function *Fn = MF->getFunction();
|
|
if (LandingPadSuccs.size() > 1 &&
|
|
!(AsmInfo &&
|
|
AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
|
|
BB && isa<SwitchInst>(BB->getTerminator())) &&
|
|
!isFuncletEHPersonality(classifyEHPersonality(Fn->getPersonalityFn())))
|
|
report("MBB has more than one landing pad successor", MBB);
|
|
|
|
// Call AnalyzeBranch. If it succeeds, there several more conditions to check.
|
|
MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
|
|
SmallVector<MachineOperand, 4> Cond;
|
|
if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
|
|
Cond)) {
|
|
// Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
|
|
// check whether its answers match up with reality.
|
|
if (!TBB && !FBB) {
|
|
// Block falls through to its successor.
|
|
MachineFunction::const_iterator MBBI = MBB->getIterator();
|
|
++MBBI;
|
|
if (MBBI == MF->end()) {
|
|
// It's possible that the block legitimately ends with a noreturn
|
|
// call or an unreachable, in which case it won't actually fall
|
|
// out the bottom of the function.
|
|
} else if (MBB->succ_size() == LandingPadSuccs.size()) {
|
|
// It's possible that the block legitimately ends with a noreturn
|
|
// call or an unreachable, in which case it won't actuall fall
|
|
// out of the block.
|
|
} else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
|
|
report("MBB exits via unconditional fall-through but doesn't have "
|
|
"exactly one CFG successor!", MBB);
|
|
} else if (!MBB->isSuccessor(&*MBBI)) {
|
|
report("MBB exits via unconditional fall-through but its successor "
|
|
"differs from its CFG successor!", MBB);
|
|
}
|
|
if (!MBB->empty() && MBB->back().isBarrier() &&
|
|
!TII->isPredicated(MBB->back())) {
|
|
report("MBB exits via unconditional fall-through but ends with a "
|
|
"barrier instruction!", MBB);
|
|
}
|
|
if (!Cond.empty()) {
|
|
report("MBB exits via unconditional fall-through but has a condition!",
|
|
MBB);
|
|
}
|
|
} else if (TBB && !FBB && Cond.empty()) {
|
|
// Block unconditionally branches somewhere.
|
|
// If the block has exactly one successor, that happens to be a
|
|
// landingpad, accept it as valid control flow.
|
|
if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
|
|
(MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
|
|
*MBB->succ_begin() != *LandingPadSuccs.begin())) {
|
|
report("MBB exits via unconditional branch but doesn't have "
|
|
"exactly one CFG successor!", MBB);
|
|
} else if (!MBB->isSuccessor(TBB)) {
|
|
report("MBB exits via unconditional branch but the CFG "
|
|
"successor doesn't match the actual successor!", MBB);
|
|
}
|
|
if (MBB->empty()) {
|
|
report("MBB exits via unconditional branch but doesn't contain "
|
|
"any instructions!", MBB);
|
|
} else if (!MBB->back().isBarrier()) {
|
|
report("MBB exits via unconditional branch but doesn't end with a "
|
|
"barrier instruction!", MBB);
|
|
} else if (!MBB->back().isTerminator()) {
|
|
report("MBB exits via unconditional branch but the branch isn't a "
|
|
"terminator instruction!", MBB);
|
|
}
|
|
} else if (TBB && !FBB && !Cond.empty()) {
|
|
// Block conditionally branches somewhere, otherwise falls through.
|
|
MachineFunction::const_iterator MBBI = MBB->getIterator();
|
|
++MBBI;
|
|
if (MBBI == MF->end()) {
|
|
report("MBB conditionally falls through out of function!", MBB);
|
|
} else if (MBB->succ_size() == 1) {
|
|
// A conditional branch with only one successor is weird, but allowed.
|
|
if (&*MBBI != TBB)
|
|
report("MBB exits via conditional branch/fall-through but only has "
|
|
"one CFG successor!", MBB);
|
|
else if (TBB != *MBB->succ_begin())
|
|
report("MBB exits via conditional branch/fall-through but the CFG "
|
|
"successor don't match the actual successor!", MBB);
|
|
} else if (MBB->succ_size() != 2) {
|
|
report("MBB exits via conditional branch/fall-through but doesn't have "
|
|
"exactly two CFG successors!", MBB);
|
|
} else if (!matchPair(MBB->succ_begin(), TBB, &*MBBI)) {
|
|
report("MBB exits via conditional branch/fall-through but the CFG "
|
|
"successors don't match the actual successors!", MBB);
|
|
}
|
|
if (MBB->empty()) {
|
|
report("MBB exits via conditional branch/fall-through but doesn't "
|
|
"contain any instructions!", MBB);
|
|
} else if (MBB->back().isBarrier()) {
|
|
report("MBB exits via conditional branch/fall-through but ends with a "
|
|
"barrier instruction!", MBB);
|
|
} else if (!MBB->back().isTerminator()) {
|
|
report("MBB exits via conditional branch/fall-through but the branch "
|
|
"isn't a terminator instruction!", MBB);
|
|
}
|
|
} else if (TBB && FBB) {
|
|
// Block conditionally branches somewhere, otherwise branches
|
|
// somewhere else.
|
|
if (MBB->succ_size() == 1) {
|
|
// A conditional branch with only one successor is weird, but allowed.
|
|
if (FBB != TBB)
|
|
report("MBB exits via conditional branch/branch through but only has "
|
|
"one CFG successor!", MBB);
|
|
else if (TBB != *MBB->succ_begin())
|
|
report("MBB exits via conditional branch/branch through but the CFG "
|
|
"successor don't match the actual successor!", MBB);
|
|
} else if (MBB->succ_size() != 2) {
|
|
report("MBB exits via conditional branch/branch but doesn't have "
|
|
"exactly two CFG successors!", MBB);
|
|
} else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
|
|
report("MBB exits via conditional branch/branch but the CFG "
|
|
"successors don't match the actual successors!", MBB);
|
|
}
|
|
if (MBB->empty()) {
|
|
report("MBB exits via conditional branch/branch but doesn't "
|
|
"contain any instructions!", MBB);
|
|
} else if (!MBB->back().isBarrier()) {
|
|
report("MBB exits via conditional branch/branch but doesn't end with a "
|
|
"barrier instruction!", MBB);
|
|
} else if (!MBB->back().isTerminator()) {
|
|
report("MBB exits via conditional branch/branch but the branch "
|
|
"isn't a terminator instruction!", MBB);
|
|
}
|
|
if (Cond.empty()) {
|
|
report("MBB exits via conditinal branch/branch but there's no "
|
|
"condition!", MBB);
|
|
}
|
|
} else {
|
|
report("AnalyzeBranch returned invalid data!", MBB);
|
|
}
|
|
}
|
|
|
|
regsLive.clear();
|
|
for (const auto &LI : MBB->liveins()) {
|
|
if (!TargetRegisterInfo::isPhysicalRegister(LI.PhysReg)) {
|
|
report("MBB live-in list contains non-physical register", MBB);
|
|
continue;
|
|
}
|
|
for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
|
|
SubRegs.isValid(); ++SubRegs)
|
|
regsLive.insert(*SubRegs);
|
|
}
|
|
regsLiveInButUnused = regsLive;
|
|
|
|
const MachineFrameInfo *MFI = MF->getFrameInfo();
|
|
assert(MFI && "Function has no frame info");
|
|
BitVector PR = MFI->getPristineRegs(*MF);
|
|
for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
|
|
for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
|
|
SubRegs.isValid(); ++SubRegs)
|
|
regsLive.insert(*SubRegs);
|
|
}
|
|
|
|
regsKilled.clear();
|
|
regsDefined.clear();
|
|
|
|
if (Indexes)
|
|
lastIndex = Indexes->getMBBStartIdx(MBB);
|
|
}
|
|
|
|
// This function gets called for all bundle headers, including normal
|
|
// stand-alone unbundled instructions.
|
|
void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
|
|
if (Indexes && Indexes->hasIndex(*MI)) {
|
|
SlotIndex idx = Indexes->getInstructionIndex(*MI);
|
|
if (!(idx > lastIndex)) {
|
|
report("Instruction index out of order", MI);
|
|
errs() << "Last instruction was at " << lastIndex << '\n';
|
|
}
|
|
lastIndex = idx;
|
|
}
|
|
|
|
// Ensure non-terminators don't follow terminators.
|
|
// Ignore predicated terminators formed by if conversion.
|
|
// FIXME: If conversion shouldn't need to violate this rule.
|
|
if (MI->isTerminator() && !TII->isPredicated(*MI)) {
|
|
if (!FirstTerminator)
|
|
FirstTerminator = MI;
|
|
} else if (FirstTerminator) {
|
|
report("Non-terminator instruction after the first terminator", MI);
|
|
errs() << "First terminator was:\t" << *FirstTerminator;
|
|
}
|
|
}
|
|
|
|
// The operands on an INLINEASM instruction must follow a template.
|
|
// Verify that the flag operands make sense.
|
|
void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
|
|
// The first two operands on INLINEASM are the asm string and global flags.
|
|
if (MI->getNumOperands() < 2) {
|
|
report("Too few operands on inline asm", MI);
|
|
return;
|
|
}
|
|
if (!MI->getOperand(0).isSymbol())
|
|
report("Asm string must be an external symbol", MI);
|
|
if (!MI->getOperand(1).isImm())
|
|
report("Asm flags must be an immediate", MI);
|
|
// Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
|
|
// Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
|
|
// and Extra_IsConvergent = 32.
|
|
if (!isUInt<6>(MI->getOperand(1).getImm()))
|
|
report("Unknown asm flags", &MI->getOperand(1), 1);
|
|
|
|
static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
|
|
|
|
unsigned OpNo = InlineAsm::MIOp_FirstOperand;
|
|
unsigned NumOps;
|
|
for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
|
|
const MachineOperand &MO = MI->getOperand(OpNo);
|
|
// There may be implicit ops after the fixed operands.
|
|
if (!MO.isImm())
|
|
break;
|
|
NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
|
|
}
|
|
|
|
if (OpNo > MI->getNumOperands())
|
|
report("Missing operands in last group", MI);
|
|
|
|
// An optional MDNode follows the groups.
|
|
if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
|
|
++OpNo;
|
|
|
|
// All trailing operands must be implicit registers.
|
|
for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
|
|
const MachineOperand &MO = MI->getOperand(OpNo);
|
|
if (!MO.isReg() || !MO.isImplicit())
|
|
report("Expected implicit register after groups", &MO, OpNo);
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
|
|
const MCInstrDesc &MCID = MI->getDesc();
|
|
if (MI->getNumOperands() < MCID.getNumOperands()) {
|
|
report("Too few operands", MI);
|
|
errs() << MCID.getNumOperands() << " operands expected, but "
|
|
<< MI->getNumOperands() << " given.\n";
|
|
}
|
|
|
|
// Check the tied operands.
|
|
if (MI->isInlineAsm())
|
|
verifyInlineAsm(MI);
|
|
|
|
// Check the MachineMemOperands for basic consistency.
|
|
for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
|
|
E = MI->memoperands_end(); I != E; ++I) {
|
|
if ((*I)->isLoad() && !MI->mayLoad())
|
|
report("Missing mayLoad flag", MI);
|
|
if ((*I)->isStore() && !MI->mayStore())
|
|
report("Missing mayStore flag", MI);
|
|
}
|
|
|
|
// Debug values must not have a slot index.
|
|
// Other instructions must have one, unless they are inside a bundle.
|
|
if (LiveInts) {
|
|
bool mapped = !LiveInts->isNotInMIMap(*MI);
|
|
if (MI->isDebugValue()) {
|
|
if (mapped)
|
|
report("Debug instruction has a slot index", MI);
|
|
} else if (MI->isInsideBundle()) {
|
|
if (mapped)
|
|
report("Instruction inside bundle has a slot index", MI);
|
|
} else {
|
|
if (!mapped)
|
|
report("Missing slot index", MI);
|
|
}
|
|
}
|
|
|
|
StringRef ErrorInfo;
|
|
if (!TII->verifyInstruction(*MI, ErrorInfo))
|
|
report(ErrorInfo.data(), MI);
|
|
}
|
|
|
|
void
|
|
MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
|
|
const MachineInstr *MI = MO->getParent();
|
|
const MCInstrDesc &MCID = MI->getDesc();
|
|
unsigned NumDefs = MCID.getNumDefs();
|
|
if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
|
|
NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
|
|
|
|
// The first MCID.NumDefs operands must be explicit register defines
|
|
if (MONum < NumDefs) {
|
|
const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
|
|
if (!MO->isReg())
|
|
report("Explicit definition must be a register", MO, MONum);
|
|
else if (!MO->isDef() && !MCOI.isOptionalDef())
|
|
report("Explicit definition marked as use", MO, MONum);
|
|
else if (MO->isImplicit())
|
|
report("Explicit definition marked as implicit", MO, MONum);
|
|
} else if (MONum < MCID.getNumOperands()) {
|
|
const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
|
|
// Don't check if it's the last operand in a variadic instruction. See,
|
|
// e.g., LDM_RET in the arm back end.
|
|
if (MO->isReg() &&
|
|
!(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
|
|
if (MO->isDef() && !MCOI.isOptionalDef())
|
|
report("Explicit operand marked as def", MO, MONum);
|
|
if (MO->isImplicit())
|
|
report("Explicit operand marked as implicit", MO, MONum);
|
|
}
|
|
|
|
int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
|
|
if (TiedTo != -1) {
|
|
if (!MO->isReg())
|
|
report("Tied use must be a register", MO, MONum);
|
|
else if (!MO->isTied())
|
|
report("Operand should be tied", MO, MONum);
|
|
else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
|
|
report("Tied def doesn't match MCInstrDesc", MO, MONum);
|
|
} else if (MO->isReg() && MO->isTied())
|
|
report("Explicit operand should not be tied", MO, MONum);
|
|
} else {
|
|
// ARM adds %reg0 operands to indicate predicates. We'll allow that.
|
|
if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
|
|
report("Extra explicit operand on non-variadic instruction", MO, MONum);
|
|
}
|
|
|
|
switch (MO->getType()) {
|
|
case MachineOperand::MO_Register: {
|
|
const unsigned Reg = MO->getReg();
|
|
if (!Reg)
|
|
return;
|
|
if (MRI->tracksLiveness() && !MI->isDebugValue())
|
|
checkLiveness(MO, MONum);
|
|
|
|
// Verify the consistency of tied operands.
|
|
if (MO->isTied()) {
|
|
unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
|
|
const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
|
|
if (!OtherMO.isReg())
|
|
report("Must be tied to a register", MO, MONum);
|
|
if (!OtherMO.isTied())
|
|
report("Missing tie flags on tied operand", MO, MONum);
|
|
if (MI->findTiedOperandIdx(OtherIdx) != MONum)
|
|
report("Inconsistent tie links", MO, MONum);
|
|
if (MONum < MCID.getNumDefs()) {
|
|
if (OtherIdx < MCID.getNumOperands()) {
|
|
if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
|
|
report("Explicit def tied to explicit use without tie constraint",
|
|
MO, MONum);
|
|
} else {
|
|
if (!OtherMO.isImplicit())
|
|
report("Explicit def should be tied to implicit use", MO, MONum);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Verify two-address constraints after leaving SSA form.
|
|
unsigned DefIdx;
|
|
if (!MRI->isSSA() && MO->isUse() &&
|
|
MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
|
|
Reg != MI->getOperand(DefIdx).getReg())
|
|
report("Two-address instruction operands must be identical", MO, MONum);
|
|
|
|
// Check register classes.
|
|
if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
|
|
unsigned SubIdx = MO->getSubReg();
|
|
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
if (SubIdx) {
|
|
report("Illegal subregister index for physical register", MO, MONum);
|
|
return;
|
|
}
|
|
if (const TargetRegisterClass *DRC =
|
|
TII->getRegClass(MCID, MONum, TRI, *MF)) {
|
|
if (!DRC->contains(Reg)) {
|
|
report("Illegal physical register for instruction", MO, MONum);
|
|
errs() << TRI->getName(Reg) << " is not a "
|
|
<< TRI->getRegClassName(DRC) << " register.\n";
|
|
}
|
|
}
|
|
} else {
|
|
// Virtual register.
|
|
const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
|
|
if (!RC) {
|
|
// This is a generic virtual register.
|
|
// It must have a size and it must not have a SubIdx.
|
|
unsigned Size = MRI->getSize(Reg);
|
|
if (!Size) {
|
|
report("Generic virtual register must have a size", MO, MONum);
|
|
return;
|
|
}
|
|
// Make sure the register fits into its register bank if any.
|
|
const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
|
|
if (RegBank && RegBank->getSize() < Size) {
|
|
report("Register bank is too small for virtual register", MO,
|
|
MONum);
|
|
errs() << "Register bank " << RegBank->getName() << " too small("
|
|
<< RegBank->getSize() << ") to fit " << Size << "-bits\n";
|
|
return;
|
|
}
|
|
if (SubIdx) {
|
|
report("Generic virtual register does not subregister index", MO, MONum);
|
|
return;
|
|
}
|
|
break;
|
|
}
|
|
if (SubIdx) {
|
|
const TargetRegisterClass *SRC =
|
|
TRI->getSubClassWithSubReg(RC, SubIdx);
|
|
if (!SRC) {
|
|
report("Invalid subregister index for virtual register", MO, MONum);
|
|
errs() << "Register class " << TRI->getRegClassName(RC)
|
|
<< " does not support subreg index " << SubIdx << "\n";
|
|
return;
|
|
}
|
|
if (RC != SRC) {
|
|
report("Invalid register class for subregister index", MO, MONum);
|
|
errs() << "Register class " << TRI->getRegClassName(RC)
|
|
<< " does not fully support subreg index " << SubIdx << "\n";
|
|
return;
|
|
}
|
|
}
|
|
if (const TargetRegisterClass *DRC =
|
|
TII->getRegClass(MCID, MONum, TRI, *MF)) {
|
|
if (SubIdx) {
|
|
const TargetRegisterClass *SuperRC =
|
|
TRI->getLargestLegalSuperClass(RC, *MF);
|
|
if (!SuperRC) {
|
|
report("No largest legal super class exists.", MO, MONum);
|
|
return;
|
|
}
|
|
DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
|
|
if (!DRC) {
|
|
report("No matching super-reg register class.", MO, MONum);
|
|
return;
|
|
}
|
|
}
|
|
if (!RC->hasSuperClassEq(DRC)) {
|
|
report("Illegal virtual register for instruction", MO, MONum);
|
|
errs() << "Expected a " << TRI->getRegClassName(DRC)
|
|
<< " register, but got a " << TRI->getRegClassName(RC)
|
|
<< " register\n";
|
|
}
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
case MachineOperand::MO_RegisterMask:
|
|
regMasks.push_back(MO->getRegMask());
|
|
break;
|
|
|
|
case MachineOperand::MO_MachineBasicBlock:
|
|
if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
|
|
report("PHI operand is not in the CFG", MO, MONum);
|
|
break;
|
|
|
|
case MachineOperand::MO_FrameIndex:
|
|
if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
|
|
LiveInts && !LiveInts->isNotInMIMap(*MI)) {
|
|
int FI = MO->getIndex();
|
|
LiveInterval &LI = LiveStks->getInterval(FI);
|
|
SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
|
|
|
|
bool stores = MI->mayStore();
|
|
bool loads = MI->mayLoad();
|
|
// For a memory-to-memory move, we need to check if the frame
|
|
// index is used for storing or loading, by inspecting the
|
|
// memory operands.
|
|
if (stores && loads) {
|
|
for (auto *MMO : MI->memoperands()) {
|
|
const PseudoSourceValue *PSV = MMO->getPseudoValue();
|
|
if (PSV == nullptr) continue;
|
|
const FixedStackPseudoSourceValue *Value =
|
|
dyn_cast<FixedStackPseudoSourceValue>(PSV);
|
|
if (Value == nullptr) continue;
|
|
if (Value->getFrameIndex() != FI) continue;
|
|
|
|
if (MMO->isStore())
|
|
loads = false;
|
|
else
|
|
stores = false;
|
|
break;
|
|
}
|
|
if (loads == stores)
|
|
report("Missing fixed stack memoperand.", MI);
|
|
}
|
|
if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
|
|
report("Instruction loads from dead spill slot", MO, MONum);
|
|
errs() << "Live stack: " << LI << '\n';
|
|
}
|
|
if (stores && !LI.liveAt(Idx.getRegSlot())) {
|
|
report("Instruction stores to dead spill slot", MO, MONum);
|
|
errs() << "Live stack: " << LI << '\n';
|
|
}
|
|
}
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
|
|
unsigned MONum, SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
|
|
LaneBitmask LaneMask) {
|
|
LiveQueryResult LRQ = LR.Query(UseIdx);
|
|
// Check if we have a segment at the use, note however that we only need one
|
|
// live subregister range, the others may be dead.
|
|
if (!LRQ.valueIn() && LaneMask == 0) {
|
|
report("No live segment at use", MO, MONum);
|
|
report_context_liverange(LR);
|
|
report_context_vreg_regunit(VRegOrUnit);
|
|
report_context(UseIdx);
|
|
}
|
|
if (MO->isKill() && !LRQ.isKill()) {
|
|
report("Live range continues after kill flag", MO, MONum);
|
|
report_context_liverange(LR);
|
|
report_context_vreg_regunit(VRegOrUnit);
|
|
if (LaneMask != 0)
|
|
report_context_lanemask(LaneMask);
|
|
report_context(UseIdx);
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
|
|
unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
|
|
LaneBitmask LaneMask) {
|
|
if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
|
|
assert(VNI && "NULL valno is not allowed");
|
|
if (VNI->def != DefIdx) {
|
|
report("Inconsistent valno->def", MO, MONum);
|
|
report_context_liverange(LR);
|
|
report_context_vreg_regunit(VRegOrUnit);
|
|
if (LaneMask != 0)
|
|
report_context_lanemask(LaneMask);
|
|
report_context(*VNI);
|
|
report_context(DefIdx);
|
|
}
|
|
} else {
|
|
report("No live segment at def", MO, MONum);
|
|
report_context_liverange(LR);
|
|
report_context_vreg_regunit(VRegOrUnit);
|
|
if (LaneMask != 0)
|
|
report_context_lanemask(LaneMask);
|
|
report_context(DefIdx);
|
|
}
|
|
// Check that, if the dead def flag is present, LiveInts agree.
|
|
if (MO->isDead()) {
|
|
LiveQueryResult LRQ = LR.Query(DefIdx);
|
|
if (!LRQ.isDeadDef()) {
|
|
// In case of physregs we can have a non-dead definition on another
|
|
// operand.
|
|
bool otherDef = false;
|
|
if (!TargetRegisterInfo::isVirtualRegister(VRegOrUnit)) {
|
|
const MachineInstr &MI = *MO->getParent();
|
|
for (const MachineOperand &MO : MI.operands()) {
|
|
if (!MO.isReg() || !MO.isDef() || MO.isDead())
|
|
continue;
|
|
unsigned Reg = MO.getReg();
|
|
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
|
|
if (*Units == VRegOrUnit) {
|
|
otherDef = true;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!otherDef) {
|
|
report("Live range continues after dead def flag", MO, MONum);
|
|
report_context_liverange(LR);
|
|
report_context_vreg_regunit(VRegOrUnit);
|
|
if (LaneMask != 0)
|
|
report_context_lanemask(LaneMask);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
|
|
const MachineInstr *MI = MO->getParent();
|
|
const unsigned Reg = MO->getReg();
|
|
|
|
// Both use and def operands can read a register.
|
|
if (MO->readsReg()) {
|
|
regsLiveInButUnused.erase(Reg);
|
|
|
|
if (MO->isKill())
|
|
addRegWithSubRegs(regsKilled, Reg);
|
|
|
|
// Check that LiveVars knows this kill.
|
|
if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
|
|
MO->isKill()) {
|
|
LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
|
|
if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
|
|
report("Kill missing from LiveVariables", MO, MONum);
|
|
}
|
|
|
|
// Check LiveInts liveness and kill.
|
|
if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
|
|
SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
|
|
// Check the cached regunit intervals.
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
|
|
for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
|
|
if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
|
|
checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
|
|
}
|
|
}
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
if (LiveInts->hasInterval(Reg)) {
|
|
// This is a virtual register interval.
|
|
const LiveInterval &LI = LiveInts->getInterval(Reg);
|
|
checkLivenessAtUse(MO, MONum, UseIdx, LI, Reg);
|
|
|
|
if (LI.hasSubRanges() && !MO->isDef()) {
|
|
unsigned SubRegIdx = MO->getSubReg();
|
|
LaneBitmask MOMask = SubRegIdx != 0
|
|
? TRI->getSubRegIndexLaneMask(SubRegIdx)
|
|
: MRI->getMaxLaneMaskForVReg(Reg);
|
|
LaneBitmask LiveInMask = 0;
|
|
for (const LiveInterval::SubRange &SR : LI.subranges()) {
|
|
if ((MOMask & SR.LaneMask) == 0)
|
|
continue;
|
|
checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
|
|
LiveQueryResult LRQ = SR.Query(UseIdx);
|
|
if (LRQ.valueIn())
|
|
LiveInMask |= SR.LaneMask;
|
|
}
|
|
// At least parts of the register has to be live at the use.
|
|
if ((LiveInMask & MOMask) == 0) {
|
|
report("No live subrange at use", MO, MONum);
|
|
report_context(LI);
|
|
report_context(UseIdx);
|
|
}
|
|
}
|
|
} else {
|
|
report("Virtual register has no live interval", MO, MONum);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Use of a dead register.
|
|
if (!regsLive.count(Reg)) {
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
// Reserved registers may be used even when 'dead'.
|
|
bool Bad = !isReserved(Reg);
|
|
// We are fine if just any subregister has a defined value.
|
|
if (Bad) {
|
|
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid();
|
|
++SubRegs) {
|
|
if (regsLive.count(*SubRegs)) {
|
|
Bad = false;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
// If there is an additional implicit-use of a super register we stop
|
|
// here. By definition we are fine if the super register is not
|
|
// (completely) dead, if the complete super register is dead we will
|
|
// get a report for its operand.
|
|
if (Bad) {
|
|
for (const MachineOperand &MOP : MI->uses()) {
|
|
if (!MOP.isReg())
|
|
continue;
|
|
if (!MOP.isImplicit())
|
|
continue;
|
|
for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
|
|
++SubRegs) {
|
|
if (*SubRegs == Reg) {
|
|
Bad = false;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
if (Bad)
|
|
report("Using an undefined physical register", MO, MONum);
|
|
} else if (MRI->def_empty(Reg)) {
|
|
report("Reading virtual register without a def", MO, MONum);
|
|
} else {
|
|
BBInfo &MInfo = MBBInfoMap[MI->getParent()];
|
|
// We don't know which virtual registers are live in, so only complain
|
|
// if vreg was killed in this MBB. Otherwise keep track of vregs that
|
|
// must be live in. PHI instructions are handled separately.
|
|
if (MInfo.regsKilled.count(Reg))
|
|
report("Using a killed virtual register", MO, MONum);
|
|
else if (!MI->isPHI())
|
|
MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
|
|
}
|
|
}
|
|
}
|
|
|
|
if (MO->isDef()) {
|
|
// Register defined.
|
|
// TODO: verify that earlyclobber ops are not used.
|
|
if (MO->isDead())
|
|
addRegWithSubRegs(regsDead, Reg);
|
|
else
|
|
addRegWithSubRegs(regsDefined, Reg);
|
|
|
|
// Verify SSA form.
|
|
if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
|
|
std::next(MRI->def_begin(Reg)) != MRI->def_end())
|
|
report("Multiple virtual register defs in SSA form", MO, MONum);
|
|
|
|
// Check LiveInts for a live segment, but only for virtual registers.
|
|
if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
|
|
SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
|
|
DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
if (LiveInts->hasInterval(Reg)) {
|
|
const LiveInterval &LI = LiveInts->getInterval(Reg);
|
|
checkLivenessAtDef(MO, MONum, DefIdx, LI, Reg);
|
|
|
|
if (LI.hasSubRanges()) {
|
|
unsigned SubRegIdx = MO->getSubReg();
|
|
LaneBitmask MOMask = SubRegIdx != 0
|
|
? TRI->getSubRegIndexLaneMask(SubRegIdx)
|
|
: MRI->getMaxLaneMaskForVReg(Reg);
|
|
for (const LiveInterval::SubRange &SR : LI.subranges()) {
|
|
if ((SR.LaneMask & MOMask) == 0)
|
|
continue;
|
|
checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, SR.LaneMask);
|
|
}
|
|
}
|
|
} else {
|
|
report("Virtual register has no Live interval", MO, MONum);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
|
|
}
|
|
|
|
// This function gets called after visiting all instructions in a bundle. The
|
|
// argument points to the bundle header.
|
|
// Normal stand-alone instructions are also considered 'bundles', and this
|
|
// function is called for all of them.
|
|
void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
|
|
BBInfo &MInfo = MBBInfoMap[MI->getParent()];
|
|
set_union(MInfo.regsKilled, regsKilled);
|
|
set_subtract(regsLive, regsKilled); regsKilled.clear();
|
|
// Kill any masked registers.
|
|
while (!regMasks.empty()) {
|
|
const uint32_t *Mask = regMasks.pop_back_val();
|
|
for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
|
|
if (TargetRegisterInfo::isPhysicalRegister(*I) &&
|
|
MachineOperand::clobbersPhysReg(Mask, *I))
|
|
regsDead.push_back(*I);
|
|
}
|
|
set_subtract(regsLive, regsDead); regsDead.clear();
|
|
set_union(regsLive, regsDefined); regsDefined.clear();
|
|
}
|
|
|
|
void
|
|
MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
|
|
MBBInfoMap[MBB].regsLiveOut = regsLive;
|
|
regsLive.clear();
|
|
|
|
if (Indexes) {
|
|
SlotIndex stop = Indexes->getMBBEndIdx(MBB);
|
|
if (!(stop > lastIndex)) {
|
|
report("Block ends before last instruction index", MBB);
|
|
errs() << "Block ends at " << stop
|
|
<< " last instruction was at " << lastIndex << '\n';
|
|
}
|
|
lastIndex = stop;
|
|
}
|
|
}
|
|
|
|
// Calculate the largest possible vregsPassed sets. These are the registers that
|
|
// can pass through an MBB live, but may not be live every time. It is assumed
|
|
// that all vregsPassed sets are empty before the call.
|
|
void MachineVerifier::calcRegsPassed() {
|
|
// First push live-out regs to successors' vregsPassed. Remember the MBBs that
|
|
// have any vregsPassed.
|
|
SmallPtrSet<const MachineBasicBlock*, 8> todo;
|
|
for (const auto &MBB : *MF) {
|
|
BBInfo &MInfo = MBBInfoMap[&MBB];
|
|
if (!MInfo.reachable)
|
|
continue;
|
|
for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
|
|
SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
|
|
BBInfo &SInfo = MBBInfoMap[*SuI];
|
|
if (SInfo.addPassed(MInfo.regsLiveOut))
|
|
todo.insert(*SuI);
|
|
}
|
|
}
|
|
|
|
// Iteratively push vregsPassed to successors. This will converge to the same
|
|
// final state regardless of DenseSet iteration order.
|
|
while (!todo.empty()) {
|
|
const MachineBasicBlock *MBB = *todo.begin();
|
|
todo.erase(MBB);
|
|
BBInfo &MInfo = MBBInfoMap[MBB];
|
|
for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
|
|
SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
|
|
if (*SuI == MBB)
|
|
continue;
|
|
BBInfo &SInfo = MBBInfoMap[*SuI];
|
|
if (SInfo.addPassed(MInfo.vregsPassed))
|
|
todo.insert(*SuI);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Calculate the set of virtual registers that must be passed through each basic
|
|
// block in order to satisfy the requirements of successor blocks. This is very
|
|
// similar to calcRegsPassed, only backwards.
|
|
void MachineVerifier::calcRegsRequired() {
|
|
// First push live-in regs to predecessors' vregsRequired.
|
|
SmallPtrSet<const MachineBasicBlock*, 8> todo;
|
|
for (const auto &MBB : *MF) {
|
|
BBInfo &MInfo = MBBInfoMap[&MBB];
|
|
for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
|
|
PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
|
|
BBInfo &PInfo = MBBInfoMap[*PrI];
|
|
if (PInfo.addRequired(MInfo.vregsLiveIn))
|
|
todo.insert(*PrI);
|
|
}
|
|
}
|
|
|
|
// Iteratively push vregsRequired to predecessors. This will converge to the
|
|
// same final state regardless of DenseSet iteration order.
|
|
while (!todo.empty()) {
|
|
const MachineBasicBlock *MBB = *todo.begin();
|
|
todo.erase(MBB);
|
|
BBInfo &MInfo = MBBInfoMap[MBB];
|
|
for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
|
|
PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
|
|
if (*PrI == MBB)
|
|
continue;
|
|
BBInfo &SInfo = MBBInfoMap[*PrI];
|
|
if (SInfo.addRequired(MInfo.vregsRequired))
|
|
todo.insert(*PrI);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Check PHI instructions at the beginning of MBB. It is assumed that
|
|
// calcRegsPassed has been run so BBInfo::isLiveOut is valid.
|
|
void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
|
|
SmallPtrSet<const MachineBasicBlock*, 8> seen;
|
|
for (const auto &BBI : *MBB) {
|
|
if (!BBI.isPHI())
|
|
break;
|
|
seen.clear();
|
|
|
|
for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2) {
|
|
unsigned Reg = BBI.getOperand(i).getReg();
|
|
const MachineBasicBlock *Pre = BBI.getOperand(i + 1).getMBB();
|
|
if (!Pre->isSuccessor(MBB))
|
|
continue;
|
|
seen.insert(Pre);
|
|
BBInfo &PrInfo = MBBInfoMap[Pre];
|
|
if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
|
|
report("PHI operand is not live-out from predecessor",
|
|
&BBI.getOperand(i), i);
|
|
}
|
|
|
|
// Did we see all predecessors?
|
|
for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
|
|
PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
|
|
if (!seen.count(*PrI)) {
|
|
report("Missing PHI operand", &BBI);
|
|
errs() << "BB#" << (*PrI)->getNumber()
|
|
<< " is a predecessor according to the CFG.\n";
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::visitMachineFunctionAfter() {
|
|
calcRegsPassed();
|
|
|
|
for (const auto &MBB : *MF) {
|
|
BBInfo &MInfo = MBBInfoMap[&MBB];
|
|
|
|
// Skip unreachable MBBs.
|
|
if (!MInfo.reachable)
|
|
continue;
|
|
|
|
checkPHIOps(&MBB);
|
|
}
|
|
|
|
// Now check liveness info if available
|
|
calcRegsRequired();
|
|
|
|
// Check for killed virtual registers that should be live out.
|
|
for (const auto &MBB : *MF) {
|
|
BBInfo &MInfo = MBBInfoMap[&MBB];
|
|
for (RegSet::iterator
|
|
I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
|
|
++I)
|
|
if (MInfo.regsKilled.count(*I)) {
|
|
report("Virtual register killed in block, but needed live out.", &MBB);
|
|
errs() << "Virtual register " << PrintReg(*I)
|
|
<< " is used after the block.\n";
|
|
}
|
|
}
|
|
|
|
if (!MF->empty()) {
|
|
BBInfo &MInfo = MBBInfoMap[&MF->front()];
|
|
for (RegSet::iterator
|
|
I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
|
|
++I) {
|
|
report("Virtual register defs don't dominate all uses.", MF);
|
|
report_context_vreg(*I);
|
|
}
|
|
}
|
|
|
|
if (LiveVars)
|
|
verifyLiveVariables();
|
|
if (LiveInts)
|
|
verifyLiveIntervals();
|
|
}
|
|
|
|
void MachineVerifier::verifyLiveVariables() {
|
|
assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
|
|
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
|
|
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
|
|
LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
|
|
for (const auto &MBB : *MF) {
|
|
BBInfo &MInfo = MBBInfoMap[&MBB];
|
|
|
|
// Our vregsRequired should be identical to LiveVariables' AliveBlocks
|
|
if (MInfo.vregsRequired.count(Reg)) {
|
|
if (!VI.AliveBlocks.test(MBB.getNumber())) {
|
|
report("LiveVariables: Block missing from AliveBlocks", &MBB);
|
|
errs() << "Virtual register " << PrintReg(Reg)
|
|
<< " must be live through the block.\n";
|
|
}
|
|
} else {
|
|
if (VI.AliveBlocks.test(MBB.getNumber())) {
|
|
report("LiveVariables: Block should not be in AliveBlocks", &MBB);
|
|
errs() << "Virtual register " << PrintReg(Reg)
|
|
<< " is not needed live through the block.\n";
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::verifyLiveIntervals() {
|
|
assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
|
|
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
|
|
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
|
|
|
|
// Spilling and splitting may leave unused registers around. Skip them.
|
|
if (MRI->reg_nodbg_empty(Reg))
|
|
continue;
|
|
|
|
if (!LiveInts->hasInterval(Reg)) {
|
|
report("Missing live interval for virtual register", MF);
|
|
errs() << PrintReg(Reg, TRI) << " still has defs or uses\n";
|
|
continue;
|
|
}
|
|
|
|
const LiveInterval &LI = LiveInts->getInterval(Reg);
|
|
assert(Reg == LI.reg && "Invalid reg to interval mapping");
|
|
verifyLiveInterval(LI);
|
|
}
|
|
|
|
// Verify all the cached regunit intervals.
|
|
for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
|
|
if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
|
|
verifyLiveRange(*LR, i);
|
|
}
|
|
|
|
void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
|
|
const VNInfo *VNI, unsigned Reg,
|
|
LaneBitmask LaneMask) {
|
|
if (VNI->isUnused())
|
|
return;
|
|
|
|
const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
|
|
|
|
if (!DefVNI) {
|
|
report("Value not live at VNInfo def and not marked unused", MF);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(*VNI);
|
|
return;
|
|
}
|
|
|
|
if (DefVNI != VNI) {
|
|
report("Live segment at def has different VNInfo", MF);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(*VNI);
|
|
return;
|
|
}
|
|
|
|
const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
|
|
if (!MBB) {
|
|
report("Invalid VNInfo definition index", MF);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(*VNI);
|
|
return;
|
|
}
|
|
|
|
if (VNI->isPHIDef()) {
|
|
if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
|
|
report("PHIDef VNInfo is not defined at MBB start", MBB);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(*VNI);
|
|
}
|
|
return;
|
|
}
|
|
|
|
// Non-PHI def.
|
|
const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
|
|
if (!MI) {
|
|
report("No instruction at VNInfo def index", MBB);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(*VNI);
|
|
return;
|
|
}
|
|
|
|
if (Reg != 0) {
|
|
bool hasDef = false;
|
|
bool isEarlyClobber = false;
|
|
for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
|
|
if (!MOI->isReg() || !MOI->isDef())
|
|
continue;
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
if (MOI->getReg() != Reg)
|
|
continue;
|
|
} else {
|
|
if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
|
|
!TRI->hasRegUnit(MOI->getReg(), Reg))
|
|
continue;
|
|
}
|
|
if (LaneMask != 0 &&
|
|
(TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask) == 0)
|
|
continue;
|
|
hasDef = true;
|
|
if (MOI->isEarlyClobber())
|
|
isEarlyClobber = true;
|
|
}
|
|
|
|
if (!hasDef) {
|
|
report("Defining instruction does not modify register", MI);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(*VNI);
|
|
}
|
|
|
|
// Early clobber defs begin at USE slots, but other defs must begin at
|
|
// DEF slots.
|
|
if (isEarlyClobber) {
|
|
if (!VNI->def.isEarlyClobber()) {
|
|
report("Early clobber def must be at an early-clobber slot", MBB);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(*VNI);
|
|
}
|
|
} else if (!VNI->def.isRegister()) {
|
|
report("Non-PHI, non-early clobber def must be at a register slot", MBB);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(*VNI);
|
|
}
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
|
|
const LiveRange::const_iterator I,
|
|
unsigned Reg, LaneBitmask LaneMask)
|
|
{
|
|
const LiveRange::Segment &S = *I;
|
|
const VNInfo *VNI = S.valno;
|
|
assert(VNI && "Live segment has no valno");
|
|
|
|
if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
|
|
report("Foreign valno in live segment", MF);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(S);
|
|
report_context(*VNI);
|
|
}
|
|
|
|
if (VNI->isUnused()) {
|
|
report("Live segment valno is marked unused", MF);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(S);
|
|
}
|
|
|
|
const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
|
|
if (!MBB) {
|
|
report("Bad start of live segment, no basic block", MF);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(S);
|
|
return;
|
|
}
|
|
SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
|
|
if (S.start != MBBStartIdx && S.start != VNI->def) {
|
|
report("Live segment must begin at MBB entry or valno def", MBB);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(S);
|
|
}
|
|
|
|
const MachineBasicBlock *EndMBB =
|
|
LiveInts->getMBBFromIndex(S.end.getPrevSlot());
|
|
if (!EndMBB) {
|
|
report("Bad end of live segment, no basic block", MF);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(S);
|
|
return;
|
|
}
|
|
|
|
// No more checks for live-out segments.
|
|
if (S.end == LiveInts->getMBBEndIdx(EndMBB))
|
|
return;
|
|
|
|
// RegUnit intervals are allowed dead phis.
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg) && VNI->isPHIDef() &&
|
|
S.start == VNI->def && S.end == VNI->def.getDeadSlot())
|
|
return;
|
|
|
|
// The live segment is ending inside EndMBB
|
|
const MachineInstr *MI =
|
|
LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
|
|
if (!MI) {
|
|
report("Live segment doesn't end at a valid instruction", EndMBB);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(S);
|
|
return;
|
|
}
|
|
|
|
// The block slot must refer to a basic block boundary.
|
|
if (S.end.isBlock()) {
|
|
report("Live segment ends at B slot of an instruction", EndMBB);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(S);
|
|
}
|
|
|
|
if (S.end.isDead()) {
|
|
// Segment ends on the dead slot.
|
|
// That means there must be a dead def.
|
|
if (!SlotIndex::isSameInstr(S.start, S.end)) {
|
|
report("Live segment ending at dead slot spans instructions", EndMBB);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(S);
|
|
}
|
|
}
|
|
|
|
// A live segment can only end at an early-clobber slot if it is being
|
|
// redefined by an early-clobber def.
|
|
if (S.end.isEarlyClobber()) {
|
|
if (I+1 == LR.end() || (I+1)->start != S.end) {
|
|
report("Live segment ending at early clobber slot must be "
|
|
"redefined by an EC def in the same instruction", EndMBB);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(S);
|
|
}
|
|
}
|
|
|
|
// The following checks only apply to virtual registers. Physreg liveness
|
|
// is too weird to check.
|
|
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
// A live segment can end with either a redefinition, a kill flag on a
|
|
// use, or a dead flag on a def.
|
|
bool hasRead = false;
|
|
bool hasSubRegDef = false;
|
|
bool hasDeadDef = false;
|
|
for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
|
|
if (!MOI->isReg() || MOI->getReg() != Reg)
|
|
continue;
|
|
if (LaneMask != 0 &&
|
|
(LaneMask & TRI->getSubRegIndexLaneMask(MOI->getSubReg())) == 0)
|
|
continue;
|
|
if (MOI->isDef()) {
|
|
if (MOI->getSubReg() != 0)
|
|
hasSubRegDef = true;
|
|
if (MOI->isDead())
|
|
hasDeadDef = true;
|
|
}
|
|
if (MOI->readsReg())
|
|
hasRead = true;
|
|
}
|
|
if (S.end.isDead()) {
|
|
// Make sure that the corresponding machine operand for a "dead" live
|
|
// range has the dead flag. We cannot perform this check for subregister
|
|
// liveranges as partially dead values are allowed.
|
|
if (LaneMask == 0 && !hasDeadDef) {
|
|
report("Instruction ending live segment on dead slot has no dead flag",
|
|
MI);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(S);
|
|
}
|
|
} else {
|
|
if (!hasRead) {
|
|
// When tracking subregister liveness, the main range must start new
|
|
// values on partial register writes, even if there is no read.
|
|
if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask != 0 ||
|
|
!hasSubRegDef) {
|
|
report("Instruction ending live segment doesn't read the register",
|
|
MI);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(S);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Now check all the basic blocks in this live segment.
|
|
MachineFunction::const_iterator MFI = MBB->getIterator();
|
|
// Is this live segment the beginning of a non-PHIDef VN?
|
|
if (S.start == VNI->def && !VNI->isPHIDef()) {
|
|
// Not live-in to any blocks.
|
|
if (MBB == EndMBB)
|
|
return;
|
|
// Skip this block.
|
|
++MFI;
|
|
}
|
|
for (;;) {
|
|
assert(LiveInts->isLiveInToMBB(LR, &*MFI));
|
|
// We don't know how to track physregs into a landing pad.
|
|
if (!TargetRegisterInfo::isVirtualRegister(Reg) &&
|
|
MFI->isEHPad()) {
|
|
if (&*MFI == EndMBB)
|
|
break;
|
|
++MFI;
|
|
continue;
|
|
}
|
|
|
|
// Is VNI a PHI-def in the current block?
|
|
bool IsPHI = VNI->isPHIDef() &&
|
|
VNI->def == LiveInts->getMBBStartIdx(&*MFI);
|
|
|
|
// Check that VNI is live-out of all predecessors.
|
|
for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
|
|
PE = MFI->pred_end(); PI != PE; ++PI) {
|
|
SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
|
|
const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
|
|
|
|
// All predecessors must have a live-out value if this is not a
|
|
// subregister liverange.
|
|
if (!PVNI && LaneMask == 0) {
|
|
report("Register not marked live out of predecessor", *PI);
|
|
report_context(LR, Reg, LaneMask);
|
|
report_context(*VNI);
|
|
errs() << " live into BB#" << MFI->getNumber()
|
|
<< '@' << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
|
|
<< PEnd << '\n';
|
|
continue;
|
|
}
|
|
|
|
// Only PHI-defs can take different predecessor values.
|
|
if (!IsPHI && PVNI != VNI) {
|
|
report("Different value live out of predecessor", *PI);
|
|
report_context(LR, Reg, LaneMask);
|
|
errs() << "Valno #" << PVNI->id << " live out of BB#"
|
|
<< (*PI)->getNumber() << '@' << PEnd << "\nValno #" << VNI->id
|
|
<< " live into BB#" << MFI->getNumber() << '@'
|
|
<< LiveInts->getMBBStartIdx(&*MFI) << '\n';
|
|
}
|
|
}
|
|
if (&*MFI == EndMBB)
|
|
break;
|
|
++MFI;
|
|
}
|
|
}
|
|
|
|
void MachineVerifier::verifyLiveRange(const LiveRange &LR, unsigned Reg,
|
|
LaneBitmask LaneMask) {
|
|
for (const VNInfo *VNI : LR.valnos)
|
|
verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
|
|
|
|
for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
|
|
verifyLiveRangeSegment(LR, I, Reg, LaneMask);
|
|
}
|
|
|
|
void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
|
|
unsigned Reg = LI.reg;
|
|
assert(TargetRegisterInfo::isVirtualRegister(Reg));
|
|
verifyLiveRange(LI, Reg);
|
|
|
|
LaneBitmask Mask = 0;
|
|
LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
|
|
for (const LiveInterval::SubRange &SR : LI.subranges()) {
|
|
if ((Mask & SR.LaneMask) != 0) {
|
|
report("Lane masks of sub ranges overlap in live interval", MF);
|
|
report_context(LI);
|
|
}
|
|
if ((SR.LaneMask & ~MaxMask) != 0) {
|
|
report("Subrange lanemask is invalid", MF);
|
|
report_context(LI);
|
|
}
|
|
if (SR.empty()) {
|
|
report("Subrange must not be empty", MF);
|
|
report_context(SR, LI.reg, SR.LaneMask);
|
|
}
|
|
Mask |= SR.LaneMask;
|
|
verifyLiveRange(SR, LI.reg, SR.LaneMask);
|
|
if (!LI.covers(SR)) {
|
|
report("A Subrange is not covered by the main range", MF);
|
|
report_context(LI);
|
|
}
|
|
}
|
|
|
|
// Check the LI only has one connected component.
|
|
ConnectedVNInfoEqClasses ConEQ(*LiveInts);
|
|
unsigned NumComp = ConEQ.Classify(LI);
|
|
if (NumComp > 1) {
|
|
report("Multiple connected components in live interval", MF);
|
|
report_context(LI);
|
|
for (unsigned comp = 0; comp != NumComp; ++comp) {
|
|
errs() << comp << ": valnos";
|
|
for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
|
|
E = LI.vni_end(); I!=E; ++I)
|
|
if (comp == ConEQ.getEqClass(*I))
|
|
errs() << ' ' << (*I)->id;
|
|
errs() << '\n';
|
|
}
|
|
}
|
|
}
|
|
|
|
namespace {
|
|
// FrameSetup and FrameDestroy can have zero adjustment, so using a single
|
|
// integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
|
|
// value is zero.
|
|
// We use a bool plus an integer to capture the stack state.
|
|
struct StackStateOfBB {
|
|
StackStateOfBB() : EntryValue(0), ExitValue(0), EntryIsSetup(false),
|
|
ExitIsSetup(false) { }
|
|
StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
|
|
EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
|
|
ExitIsSetup(ExitSetup) { }
|
|
// Can be negative, which means we are setting up a frame.
|
|
int EntryValue;
|
|
int ExitValue;
|
|
bool EntryIsSetup;
|
|
bool ExitIsSetup;
|
|
};
|
|
}
|
|
|
|
/// Make sure on every path through the CFG, a FrameSetup <n> is always followed
|
|
/// by a FrameDestroy <n>, stack adjustments are identical on all
|
|
/// CFG edges to a merge point, and frame is destroyed at end of a return block.
|
|
void MachineVerifier::verifyStackFrame() {
|
|
unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
|
|
unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
|
|
|
|
SmallVector<StackStateOfBB, 8> SPState;
|
|
SPState.resize(MF->getNumBlockIDs());
|
|
SmallPtrSet<const MachineBasicBlock*, 8> Reachable;
|
|
|
|
// Visit the MBBs in DFS order.
|
|
for (df_ext_iterator<const MachineFunction*,
|
|
SmallPtrSet<const MachineBasicBlock*, 8> >
|
|
DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
|
|
DFI != DFE; ++DFI) {
|
|
const MachineBasicBlock *MBB = *DFI;
|
|
|
|
StackStateOfBB BBState;
|
|
// Check the exit state of the DFS stack predecessor.
|
|
if (DFI.getPathLength() >= 2) {
|
|
const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
|
|
assert(Reachable.count(StackPred) &&
|
|
"DFS stack predecessor is already visited.\n");
|
|
BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
|
|
BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
|
|
BBState.ExitValue = BBState.EntryValue;
|
|
BBState.ExitIsSetup = BBState.EntryIsSetup;
|
|
}
|
|
|
|
// Update stack state by checking contents of MBB.
|
|
for (const auto &I : *MBB) {
|
|
if (I.getOpcode() == FrameSetupOpcode) {
|
|
// The first operand of a FrameOpcode should be i32.
|
|
int Size = I.getOperand(0).getImm();
|
|
assert(Size >= 0 &&
|
|
"Value should be non-negative in FrameSetup and FrameDestroy.\n");
|
|
|
|
if (BBState.ExitIsSetup)
|
|
report("FrameSetup is after another FrameSetup", &I);
|
|
BBState.ExitValue -= Size;
|
|
BBState.ExitIsSetup = true;
|
|
}
|
|
|
|
if (I.getOpcode() == FrameDestroyOpcode) {
|
|
// The first operand of a FrameOpcode should be i32.
|
|
int Size = I.getOperand(0).getImm();
|
|
assert(Size >= 0 &&
|
|
"Value should be non-negative in FrameSetup and FrameDestroy.\n");
|
|
|
|
if (!BBState.ExitIsSetup)
|
|
report("FrameDestroy is not after a FrameSetup", &I);
|
|
int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
|
|
BBState.ExitValue;
|
|
if (BBState.ExitIsSetup && AbsSPAdj != Size) {
|
|
report("FrameDestroy <n> is after FrameSetup <m>", &I);
|
|
errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
|
|
<< AbsSPAdj << ">.\n";
|
|
}
|
|
BBState.ExitValue += Size;
|
|
BBState.ExitIsSetup = false;
|
|
}
|
|
}
|
|
SPState[MBB->getNumber()] = BBState;
|
|
|
|
// Make sure the exit state of any predecessor is consistent with the entry
|
|
// state.
|
|
for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
|
|
E = MBB->pred_end(); I != E; ++I) {
|
|
if (Reachable.count(*I) &&
|
|
(SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
|
|
SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
|
|
report("The exit stack state of a predecessor is inconsistent.", MBB);
|
|
errs() << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
|
|
<< SPState[(*I)->getNumber()].ExitValue << ", "
|
|
<< SPState[(*I)->getNumber()].ExitIsSetup
|
|
<< "), while BB#" << MBB->getNumber() << " has entry state ("
|
|
<< BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
|
|
}
|
|
}
|
|
|
|
// Make sure the entry state of any successor is consistent with the exit
|
|
// state.
|
|
for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
|
|
E = MBB->succ_end(); I != E; ++I) {
|
|
if (Reachable.count(*I) &&
|
|
(SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
|
|
SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
|
|
report("The entry stack state of a successor is inconsistent.", MBB);
|
|
errs() << "Successor BB#" << (*I)->getNumber() << " has entry state ("
|
|
<< SPState[(*I)->getNumber()].EntryValue << ", "
|
|
<< SPState[(*I)->getNumber()].EntryIsSetup
|
|
<< "), while BB#" << MBB->getNumber() << " has exit state ("
|
|
<< BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
|
|
}
|
|
}
|
|
|
|
// Make sure a basic block with return ends with zero stack adjustment.
|
|
if (!MBB->empty() && MBB->back().isReturn()) {
|
|
if (BBState.ExitIsSetup)
|
|
report("A return block ends with a FrameSetup.", MBB);
|
|
if (BBState.ExitValue)
|
|
report("A return block ends with a nonzero stack adjustment.", MBB);
|
|
}
|
|
}
|
|
}
|