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135 lines
4.0 KiB
135 lines
4.0 KiB
//==- HexagonSystemInst.td - System Instructions for Hexagon -*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hexagon instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Cache manipulation instructions.
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//===----------------------------------------------------------------------===//
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let mayStore = 1 in
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class ST_MISC_CACHEOP<dag outs, dag ins,
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string asmstr, list<dag> pattern = [],
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bits<3> amode, bits<3> type, bits<1> un>
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: ST0Inst<outs, ins, asmstr, pattern, "", ST_tc_ld_SLOT0> {
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bits<5> Rs;
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bits<5> Rt;
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bits<5> Rd;
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let Inst{31-28} = 0b1010;
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let Inst{27-25} = amode;
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let Inst{24-22} = type;
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let Inst{21} = un;
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let Inst{20-16} = Rs;
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let Inst{12-8} = Rt;
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let Inst{4-0} = Rd;
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}
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let mayStore = 1 in
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class ST_MISC_CACHEOP_SYS<dag outs, dag ins,
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string asmstr, list<dag> pattern = [],
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bits<3> amode, bits<3> type, bits<1> un>
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: SYSInst<outs, ins, asmstr, pattern, ""> {
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bits<5> Rs;
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bits<5> Rt;
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bits<5> Rd;
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let Inst{31-28} = 0b1010;
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let Inst{27-25} = amode;
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let Inst{24-22} = type;
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let Inst{21} = un;
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let Inst{20-16} = Rs;
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let Inst{12-8} = Rt;
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let Inst{4-0} = Rd;
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}
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let isSolo = 1, Rs = 0, Rt = 0, Rd = 0 in {
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def Y2_syncht: ST_MISC_CACHEOP <(outs), (ins),
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"syncht" , [], 0b100, 0b001, 0b0>;
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}
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let Rt = 0, Rd = 0 in {
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let isSoloAin1 = 1 in {
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def Y2_dccleana: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs),
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"dccleana($Rs)", [], 0b000, 0b000, 0b0>;
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def Y2_dcinva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs),
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"dcinva($Rs)", [], 0b000, 0b000, 0b1>;
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def Y2_dccleaninva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs),
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"dccleaninva($Rs)", [], 0b000, 0b001, 0b0>;
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}
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}
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let isSoloAX = 1, hasSideEffects = 1, Rd = 0 in {
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def Y4_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, IntRegs:$Rt),
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"l2fetch($Rs, $Rt)", [], 0b011, 0b000, 0b0>;
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def Y5_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, DoubleRegs:$Rt),
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"l2fetch($Rs, $Rt)", [], 0b011, 0b010, 0b0>;
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}
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let hasSideEffects = 0, isSolo = 1 in
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class Y2_INVALIDATE_CACHE<string mnemonic, bit MajOp>
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: JRInst <
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(outs), (ins IntRegs:$Rs),
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#mnemonic#"($Rs)" > {
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bits<5> Rs;
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let IClass = 0b0101;
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let Inst{27-21} = 0b0110110;
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let Inst{20-16} = Rs;
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let Inst{13-12} = 0b00;
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let Inst{11} = MajOp;
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}
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// Instruction cache invalidate
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def Y2_icinva : Y2_INVALIDATE_CACHE<"icinva", 0b0>;
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// Zero an aligned 32-byte cacheline.
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let isSoloAin1 = 1 in
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def Y2_dczeroa: ST0Inst <(outs), (ins IntRegs:$Rs),
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"dczeroa($Rs)"> {
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bits<5> Rs;
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let IClass = 0b1010;
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let Inst{27-21} = 0b0000110;
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let Inst{13} = 0b0;
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let Inst{20-16} = Rs;
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}
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// Memory synchronization.
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let hasSideEffects = 0, isSolo = 1 in
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def Y2_isync: JRInst <(outs), (ins),
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"isync"> {
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let IClass = 0b0101;
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let Inst{27-16} = 0b011111000000;
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let Inst{13} = 0b0;
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let Inst{9-0} = 0b0000000010;
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}
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//===----------------------------------------------------------------------===//
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// System/User instructions.
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//===----------------------------------------------------------------------===//
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// traps and pause
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let hasSideEffects = 0, isSolo = 1 in
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class J2_MISC_TRAP_PAUSE<string mnemonic, bits<2> MajOp>
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: JRInst
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<(outs), (ins u8Imm:$u8),
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#mnemonic#"(#$u8)"> {
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bits<8> u8;
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let IClass = 0b0101;
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let Inst{27-24} = 0b0100;
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let Inst{23-22} = MajOp;
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let Inst{12-8} = u8{7-3};
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let Inst{4-2} = u8{2-0};
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}
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def J2_trap0 : J2_MISC_TRAP_PAUSE<"trap0", 0b00>;
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def J2_trap1 : J2_MISC_TRAP_PAUSE<"trap1", 0b10>;
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def J2_pause : J2_MISC_TRAP_PAUSE<"pause", 0b01>;
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