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323 lines
11 KiB
323 lines
11 KiB
//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Hexagon target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonTargetMachine.h"
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#include "Hexagon.h"
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#include "HexagonISelLowering.h"
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#include "HexagonMachineScheduler.h"
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#include "HexagonTargetObjectFile.h"
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#include "HexagonTargetTransformInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
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cl::init(true), cl::desc("Enable RDF-based optimizations"));
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static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
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cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
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static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon Addressing Mode Optimization"));
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static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon CFG Optimization"));
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static cl::opt<bool> DisableStoreWidening("disable-store-widen",
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cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
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static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
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cl::init(true), cl::Hidden, cl::ZeroOrMore,
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cl::desc("Early expansion of MUX"));
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static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
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cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
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static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
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cl::Hidden, cl::desc("Generate \"insert\" instructions"));
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static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
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cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
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static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
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cl::Hidden, cl::desc("Generate \"extract\" instructions"));
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static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
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cl::desc("Enable converting conditional transfers into MUX instructions"));
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static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
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cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
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"predicate instructions"));
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static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
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cl::desc("Disable splitting double registers"));
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static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
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cl::Hidden, cl::desc("Bit simplification"));
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static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
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cl::Hidden, cl::desc("Loop rescheduling"));
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static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
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cl::Hidden, cl::desc("Disable backend optimizations"));
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/// HexagonTargetMachineModule - Note that this is used on hosts that
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/// cannot link in a library unless there are references into the
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/// library. In particular, it seems that it is not possible to get
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/// things to work on Win32 without this. Though it is unused, do not
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/// remove it.
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extern "C" int HexagonTargetMachineModule;
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int HexagonTargetMachineModule = 0;
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extern "C" void LLVMInitializeHexagonTarget() {
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// Register the target.
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RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
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}
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static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
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return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
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}
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static MachineSchedRegistry
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SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
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createVLIWMachineSched);
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namespace llvm {
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FunctionPass *createHexagonBitSimplify();
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FunctionPass *createHexagonBranchRelaxation();
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FunctionPass *createHexagonCallFrameInformation();
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FunctionPass *createHexagonCFGOptimizer();
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FunctionPass *createHexagonCommonGEP();
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FunctionPass *createHexagonCopyToCombine();
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FunctionPass *createHexagonEarlyIfConversion();
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FunctionPass *createHexagonExpandCondsets();
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FunctionPass *createHexagonFixupHwLoops();
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FunctionPass *createHexagonGenExtract();
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FunctionPass *createHexagonGenInsert();
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FunctionPass *createHexagonGenMux();
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FunctionPass *createHexagonGenPredicate();
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FunctionPass *createHexagonHardwareLoops();
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FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createHexagonLoopRescheduling();
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FunctionPass *createHexagonNewValueJump();
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FunctionPass *createHexagonOptimizeSZextends();
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FunctionPass *createHexagonOptAddrMode();
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FunctionPass *createHexagonPacketizer();
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FunctionPass *createHexagonPeephole();
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FunctionPass *createHexagonRDFOpt();
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FunctionPass *createHexagonSplitConst32AndConst64();
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FunctionPass *createHexagonSplitDoubleRegs();
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FunctionPass *createHexagonStoreWidening();
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} // end namespace llvm;
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static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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if (!RM.hasValue())
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return Reloc::Static;
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return *RM;
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}
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HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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// Specify the vector alignment explicitly. For v512x1, the calculated
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// alignment would be 512*alignment(i1), which is 512 bytes, instead of
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// the required minimum of 64 bytes.
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: LLVMTargetMachine(
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T, "e-m:e-p:32:32:32-a:0-n16:32-"
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"i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
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"v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
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TT, CPU, FS, Options, getEffectiveRelocModel(RM), CM,
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(HexagonNoOpt ? CodeGenOpt::None : OL)),
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TLOF(make_unique<HexagonTargetObjectFile>()) {
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initAsmInfo();
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}
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const HexagonSubtarget *
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HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
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AttributeSet FnAttrs = F.getAttributes();
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Attribute CPUAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
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Attribute FSAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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auto &I = SubtargetMap[CPU + FS];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
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}
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return I.get();
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}
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TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
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return TargetIRAnalysis([this](const Function &F) {
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return TargetTransformInfo(HexagonTTIImpl(this, F));
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});
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}
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HexagonTargetMachine::~HexagonTargetMachine() {}
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namespace {
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/// Hexagon Code Generator Pass Configuration Options.
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class HexagonPassConfig : public TargetPassConfig {
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public:
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HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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HexagonTargetMachine &getHexagonTargetMachine() const {
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return getTM<HexagonTargetMachine>();
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}
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ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const override {
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return createVLIWMachineSched(C);
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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void addPreRegAlloc() override;
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void addPostRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new HexagonPassConfig(this, PM);
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}
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void HexagonPassConfig::addIRPasses() {
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TargetPassConfig::addIRPasses();
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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addPass(createAtomicExpandPass(TM));
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if (!NoOpt) {
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if (EnableCommGEP)
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addPass(createHexagonCommonGEP());
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// Replace certain combinations of shifts and ands with extracts.
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if (EnableGenExtract)
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addPass(createHexagonGenExtract());
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}
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}
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bool HexagonPassConfig::addInstSelector() {
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HexagonTargetMachine &TM = getHexagonTargetMachine();
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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if (!NoOpt)
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addPass(createHexagonOptimizeSZextends());
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addPass(createHexagonISelDag(TM, getOptLevel()));
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if (!NoOpt) {
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// Create logical operations on predicate registers.
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if (EnableGenPred)
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addPass(createHexagonGenPredicate(), false);
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// Rotate loops to expose bit-simplification opportunities.
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if (EnableLoopResched)
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addPass(createHexagonLoopRescheduling(), false);
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// Split double registers.
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if (!DisableHSDR)
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addPass(createHexagonSplitDoubleRegs());
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// Bit simplification.
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if (EnableBitSimplify)
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addPass(createHexagonBitSimplify(), false);
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addPass(createHexagonPeephole());
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printAndVerify("After hexagon peephole pass");
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if (EnableGenInsert)
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addPass(createHexagonGenInsert(), false);
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if (EnableEarlyIf)
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addPass(createHexagonEarlyIfConversion(), false);
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}
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return false;
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}
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void HexagonPassConfig::addPreRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None) {
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if (EnableExpandCondsets) {
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Pass *Exp = createHexagonExpandCondsets();
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insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
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}
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if (!DisableStoreWidening)
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addPass(createHexagonStoreWidening(), false);
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if (!DisableHardwareLoops)
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addPass(createHexagonHardwareLoops(), false);
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}
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if (TM->getOptLevel() >= CodeGenOpt::Default)
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addPass(&MachinePipelinerID);
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}
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void HexagonPassConfig::addPostRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None) {
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if (EnableRDFOpt)
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addPass(createHexagonRDFOpt());
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if (!DisableHexagonCFGOpt)
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addPass(createHexagonCFGOptimizer(), false);
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if (!DisableAModeOpt)
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addPass(createHexagonOptAddrMode(), false);
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}
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}
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void HexagonPassConfig::addPreSched2() {
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addPass(createHexagonCopyToCombine(), false);
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if (getOptLevel() != CodeGenOpt::None)
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addPass(&IfConverterID, false);
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addPass(createHexagonSplitConst32AndConst64());
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}
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void HexagonPassConfig::addPreEmitPass() {
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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if (!NoOpt)
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addPass(createHexagonNewValueJump(), false);
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addPass(createHexagonBranchRelaxation(), false);
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// Create Packets.
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if (!NoOpt) {
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if (!DisableHardwareLoops)
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addPass(createHexagonFixupHwLoops(), false);
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// Generate MUX from pairs of conditional transfers.
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if (EnableGenMux)
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addPass(createHexagonGenMux(), false);
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addPass(createHexagonPacketizer(), false);
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}
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// Add CFI instructions if necessary.
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addPass(createHexagonCallFrameInformation(), false);
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}
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