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464 lines
15 KiB
464 lines
15 KiB
//===----- HexagonShuffler.cpp - Instruction bundle shuffling -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements the shuffling of insns inside a bundle according to the
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// packet formation rules of the Hexagon ISA.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "hexagon-shuffle"
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#include <algorithm>
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#include <utility>
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#include "Hexagon.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "HexagonShuffler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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// Insn shuffling priority.
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class HexagonBid {
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// The priority is directly proportional to how restricted the insn is based
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// on its flexibility to run on the available slots. So, the fewer slots it
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// may run on, the higher its priority.
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enum { MAX = 360360 }; // LCD of 1/2, 1/3, 1/4,... 1/15.
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unsigned Bid;
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public:
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HexagonBid() : Bid(0){};
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HexagonBid(unsigned B) { Bid = B ? MAX / countPopulation(B) : 0; };
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// Check if the insn priority is overflowed.
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bool isSold() const { return (Bid >= MAX); };
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HexagonBid &operator+=(const HexagonBid &B) {
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Bid += B.Bid;
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return *this;
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};
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};
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// Slot shuffling allocation.
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class HexagonUnitAuction {
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HexagonBid Scores[HEXAGON_PACKET_SIZE];
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// Mask indicating which slot is unavailable.
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unsigned isSold : HEXAGON_PACKET_SIZE;
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public:
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HexagonUnitAuction() : isSold(0){};
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// Allocate slots.
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bool bid(unsigned B) {
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// Exclude already auctioned slots from the bid.
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unsigned b = B & ~isSold;
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if (b) {
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for (unsigned i = 0; i < HEXAGON_PACKET_SIZE; ++i)
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if (b & (1 << i)) {
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// Request candidate slots.
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Scores[i] += HexagonBid(b);
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isSold |= Scores[i].isSold() << i;
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}
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return true;
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;
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} else
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// Error if the desired slots are already full.
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return false;
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};
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};
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} // end anonymous namespace
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unsigned HexagonResource::setWeight(unsigned s) {
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const unsigned SlotWeight = 8;
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const unsigned MaskWeight = SlotWeight - 1;
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bool Key = (1 << s) & getUnits();
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// TODO: Improve this API so that we can prevent misuse statically.
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assert(SlotWeight * s < 32 && "Argument to setWeight too large.");
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// Calculate relative weight of the insn for the given slot, weighing it the
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// heavier the more restrictive the insn is and the lowest the slots that the
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// insn may be executed in.
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Weight =
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(Key << (SlotWeight * s)) * ((MaskWeight - countPopulation(getUnits()))
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<< countTrailingZeros(getUnits()));
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return (Weight);
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}
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void HexagonCVIResource::SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU) {
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(*TUL)[HexagonII::TypeCVI_VA] =
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UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
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(*TUL)[HexagonII::TypeCVI_VA_DV] = UnitsAndLanes(CVI_XLANE | CVI_MPY0, 2);
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(*TUL)[HexagonII::TypeCVI_VX] = UnitsAndLanes(CVI_MPY0 | CVI_MPY1, 1);
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(*TUL)[HexagonII::TypeCVI_VX_DV] = UnitsAndLanes(CVI_MPY0, 2);
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(*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1);
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(*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2);
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(*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1);
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(*TUL)[HexagonII::TypeCVI_VINLANESAT] = UnitsAndLanes(CVI_SHIFT, 1);
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(*TUL)[HexagonII::TypeCVI_VM_LD] =
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UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
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(*TUL)[HexagonII::TypeCVI_VM_TMP_LD] = UnitsAndLanes(CVI_NONE, 0);
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(*TUL)[HexagonII::TypeCVI_VM_CUR_LD] =
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UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
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(*TUL)[HexagonII::TypeCVI_VM_VP_LDU] = UnitsAndLanes(CVI_XLANE, 1);
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(*TUL)[HexagonII::TypeCVI_VM_ST] =
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UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
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(*TUL)[HexagonII::TypeCVI_VM_NEW_ST] = UnitsAndLanes(CVI_NONE, 0);
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(*TUL)[HexagonII::TypeCVI_VM_STU] = UnitsAndLanes(CVI_XLANE, 1);
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(*TUL)[HexagonII::TypeCVI_HIST] = UnitsAndLanes(CVI_XLANE, 4);
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}
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HexagonCVIResource::HexagonCVIResource(TypeUnitsAndLanes *TUL,
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MCInstrInfo const &MCII, unsigned s,
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MCInst const *id)
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: HexagonResource(s), TUL(TUL) {
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unsigned T = HexagonMCInstrInfo::getType(MCII, *id);
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if (TUL->count(T)) {
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// For an HVX insn.
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Valid = true;
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setUnits((*TUL)[T].first);
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setLanes((*TUL)[T].second);
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setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad());
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setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore());
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} else {
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// For core insns.
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Valid = false;
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setUnits(0);
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setLanes(0);
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setLoad(false);
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setStore(false);
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}
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}
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HexagonShuffler::HexagonShuffler(MCInstrInfo const &MCII,
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MCSubtargetInfo const &STI)
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: MCII(MCII), STI(STI) {
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reset();
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HexagonCVIResource::SetupTUL(&TUL, STI.getCPU());
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}
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void HexagonShuffler::reset() {
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Packet.clear();
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BundleFlags = 0;
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Error = SHUFFLE_SUCCESS;
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}
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void HexagonShuffler::append(MCInst const *ID, MCInst const *Extender,
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unsigned S, bool X) {
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HexagonInstr PI(&TUL, MCII, ID, Extender, S, X);
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Packet.push_back(PI);
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}
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/// Check that the packet is legal and enforce relative insn order.
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bool HexagonShuffler::check() {
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// Descriptive slot masks.
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const unsigned slotSingleLoad = 0x1, slotSingleStore = 0x1, slotOne = 0x2,
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slotThree = 0x8, slotFirstJump = 0x8, slotLastJump = 0x4,
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slotFirstLoadStore = 0x2, slotLastLoadStore = 0x1;
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// Highest slots for branches and stores used to keep their original order.
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unsigned slotJump = slotFirstJump;
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unsigned slotLoadStore = slotFirstLoadStore;
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// Number of branches, solo branches, indirect branches.
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unsigned jumps = 0, jump1 = 0, jumpr = 0;
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// Number of memory operations, loads, solo loads, stores, solo stores, single
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// stores.
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unsigned memory = 0, loads = 0, load0 = 0, stores = 0, store0 = 0, store1 = 0;
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// Number of HVX loads, HVX stores.
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unsigned CVIloads = 0, CVIstores = 0;
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// Number of duplex insns, solo insns.
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unsigned duplex = 0, solo = 0;
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// Number of insns restricting other insns in the packet to A and X types,
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// which is neither A or X types.
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unsigned onlyAX = 0, neitherAnorX = 0;
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// Number of insns restricting other insns in slot #1 to A type.
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unsigned onlyAin1 = 0;
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// Number of insns restricting any insn in slot #1, except A2_nop.
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unsigned onlyNo1 = 0;
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unsigned xtypeFloat = 0;
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unsigned pSlot3Cnt = 0;
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iterator slot3ISJ = end();
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// Collect information from the insns in the packet.
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for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
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MCInst const *ID = ISJ->getDesc();
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if (HexagonMCInstrInfo::isSolo(MCII, *ID))
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solo += !ISJ->isSoloException();
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else if (HexagonMCInstrInfo::isSoloAX(MCII, *ID))
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onlyAX += !ISJ->isSoloException();
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else if (HexagonMCInstrInfo::isSoloAin1(MCII, *ID))
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onlyAin1 += !ISJ->isSoloException();
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if (HexagonMCInstrInfo::getType(MCII, *ID) != HexagonII::TypeALU32 &&
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HexagonMCInstrInfo::getType(MCII, *ID) != HexagonII::TypeXTYPE)
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++neitherAnorX;
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if (HexagonMCInstrInfo::prefersSlot3(MCII, *ID)) {
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++pSlot3Cnt;
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slot3ISJ = ISJ;
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}
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switch (HexagonMCInstrInfo::getType(MCII, *ID)) {
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case HexagonII::TypeXTYPE:
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if (HexagonMCInstrInfo::isFloat(MCII, *ID))
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++xtypeFloat;
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break;
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case HexagonII::TypeJR:
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++jumpr;
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// Fall-through.
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case HexagonII::TypeJ:
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++jumps;
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break;
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case HexagonII::TypeCVI_VM_VP_LDU:
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++onlyNo1;
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case HexagonII::TypeCVI_VM_LD:
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case HexagonII::TypeCVI_VM_TMP_LD:
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case HexagonII::TypeCVI_VM_CUR_LD:
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++CVIloads;
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case HexagonII::TypeLD:
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++loads;
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++memory;
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if (ISJ->Core.getUnits() == slotSingleLoad)
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++load0;
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if (HexagonMCInstrInfo::getDesc(MCII, *ID).isReturn())
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++jumps, ++jump1; // DEALLOC_RETURN is of type LD.
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break;
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case HexagonII::TypeCVI_VM_STU:
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++onlyNo1;
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case HexagonII::TypeCVI_VM_ST:
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case HexagonII::TypeCVI_VM_NEW_ST:
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++CVIstores;
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case HexagonII::TypeST:
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++stores;
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++memory;
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if (ISJ->Core.getUnits() == slotSingleStore)
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++store0;
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break;
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case HexagonII::TypeMEMOP:
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++loads;
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++stores;
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++store1;
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++memory;
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break;
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case HexagonII::TypeNV:
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++memory; // NV insns are memory-like.
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if (HexagonMCInstrInfo::getDesc(MCII, *ID).isBranch())
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++jumps, ++jump1;
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break;
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case HexagonII::TypeCR:
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// Legacy conditional branch predicated on a register.
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case HexagonII::TypeSYSTEM:
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if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayLoad())
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++loads;
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break;
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}
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}
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// Check if the packet is legal.
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if ((load0 > 1 || store0 > 1 || CVIloads > 1 || CVIstores > 1) ||
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(duplex > 1 || (duplex && memory)) || (solo && size() > 1) ||
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(onlyAX && neitherAnorX > 1) || (onlyAX && xtypeFloat)) {
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Error = SHUFFLE_ERROR_INVALID;
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return false;
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}
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if (jump1 && jumps > 1) {
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// Error if single branch with another branch.
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Error = SHUFFLE_ERROR_BRANCHES;
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return false;
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}
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// Modify packet accordingly.
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// TODO: need to reserve slots #0 and #1 for duplex insns.
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bool bOnlySlot3 = false;
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for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
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MCInst const *ID = ISJ->getDesc();
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if (!ISJ->Core.getUnits()) {
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// Error if insn may not be executed in any slot.
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Error = SHUFFLE_ERROR_UNKNOWN;
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return false;
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}
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// Exclude from slot #1 any insn but A2_nop.
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if (HexagonMCInstrInfo::getDesc(MCII, *ID).getOpcode() != Hexagon::A2_nop)
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if (onlyNo1)
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ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne);
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// Exclude from slot #1 any insn but A-type.
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if (HexagonMCInstrInfo::getType(MCII, *ID) != HexagonII::TypeALU32)
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if (onlyAin1)
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ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne);
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// Branches must keep the original order.
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if (HexagonMCInstrInfo::getDesc(MCII, *ID).isBranch() ||
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HexagonMCInstrInfo::getDesc(MCII, *ID).isCall())
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if (jumps > 1) {
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if (jumpr || slotJump < slotLastJump) {
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// Error if indirect branch with another branch or
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// no more slots available for branches.
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Error = SHUFFLE_ERROR_BRANCHES;
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return false;
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}
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// Pin the branch to the highest slot available to it.
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ISJ->Core.setUnits(ISJ->Core.getUnits() & slotJump);
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// Update next highest slot available to branches.
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slotJump >>= 1;
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}
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// A single load must use slot #0.
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if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayLoad()) {
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if (loads == 1 && loads == memory)
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// Pin the load to slot #0.
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ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleLoad);
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}
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// A single store must use slot #0.
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if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayStore()) {
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if (!store0) {
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if (stores == 1)
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ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleStore);
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else if (stores > 1) {
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if (slotLoadStore < slotLastLoadStore) {
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// Error if no more slots available for stores.
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Error = SHUFFLE_ERROR_STORES;
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return false;
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}
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// Pin the store to the highest slot available to it.
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ISJ->Core.setUnits(ISJ->Core.getUnits() & slotLoadStore);
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// Update the next highest slot available to stores.
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slotLoadStore >>= 1;
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}
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}
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if (store1 && stores > 1) {
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// Error if a single store with another store.
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Error = SHUFFLE_ERROR_STORES;
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return false;
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}
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}
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// flag if an instruction can only be executed in slot 3
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if (ISJ->Core.getUnits() == slotThree)
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bOnlySlot3 = true;
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if (!ISJ->Core.getUnits()) {
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// Error if insn may not be executed in any slot.
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Error = SHUFFLE_ERROR_NOSLOTS;
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return false;
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}
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}
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bool validateSlots = true;
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if (bOnlySlot3 == false && pSlot3Cnt == 1 && slot3ISJ != end()) {
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// save off slot mask of instruction marked with A_PREFER_SLOT3
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// and then pin it to slot #3
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unsigned saveUnits = slot3ISJ->Core.getUnits();
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slot3ISJ->Core.setUnits(saveUnits & slotThree);
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HexagonUnitAuction AuctionCore;
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std::sort(begin(), end(), HexagonInstr::lessCore);
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// see if things ok with that instruction being pinned to slot #3
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bool bFail = false;
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for (iterator I = begin(); I != end() && bFail != true; ++I)
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if (!AuctionCore.bid(I->Core.getUnits()))
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bFail = true;
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// if yes, great, if not then restore original slot mask
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if (!bFail)
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validateSlots = false; // all good, no need to re-do auction
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else
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for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {
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MCInst const *ID = ISJ->getDesc();
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if (HexagonMCInstrInfo::prefersSlot3(MCII, *ID))
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ISJ->Core.setUnits(saveUnits);
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}
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}
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// Check if any slot, core, is over-subscribed.
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// Verify the core slot subscriptions.
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if (validateSlots) {
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HexagonUnitAuction AuctionCore;
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std::sort(begin(), end(), HexagonInstr::lessCore);
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for (iterator I = begin(); I != end(); ++I)
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if (!AuctionCore.bid(I->Core.getUnits())) {
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Error = SHUFFLE_ERROR_SLOTS;
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return false;
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}
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}
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// Verify the CVI slot subscriptions.
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{
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HexagonUnitAuction AuctionCVI;
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std::sort(begin(), end(), HexagonInstr::lessCVI);
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for (iterator I = begin(); I != end(); ++I)
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for (unsigned i = 0; i < I->CVI.getLanes(); ++i) // TODO: I->CVI.isValid?
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if (!AuctionCVI.bid(I->CVI.getUnits() << i)) {
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Error = SHUFFLE_ERROR_SLOTS;
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return false;
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}
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}
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Error = SHUFFLE_SUCCESS;
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return true;
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}
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bool HexagonShuffler::shuffle() {
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if (size() > HEXAGON_PACKET_SIZE) {
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// Ignore a packet with with more than what a packet can hold
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// or with compound or duplex insns for now.
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Error = SHUFFLE_ERROR_INVALID;
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return false;
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}
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// Check and prepare packet.
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if (size() > 1 && check())
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// Reorder the handles for each slot.
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for (unsigned nSlot = 0, emptySlots = 0; nSlot < HEXAGON_PACKET_SIZE;
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++nSlot) {
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iterator ISJ, ISK;
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unsigned slotSkip, slotWeight;
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// Prioritize the handles considering their restrictions.
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for (ISJ = ISK = Packet.begin(), slotSkip = slotWeight = 0;
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ISK != Packet.end(); ++ISK, ++slotSkip)
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if (slotSkip < nSlot - emptySlots)
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// Note which handle to begin at.
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++ISJ;
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else
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// Calculate the weight of the slot.
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slotWeight += ISK->Core.setWeight(HEXAGON_PACKET_SIZE - nSlot - 1);
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if (slotWeight)
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// Sort the packet, favoring source order,
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// beginning after the previous slot.
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std::sort(ISJ, Packet.end());
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else
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// Skip unused slot.
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++emptySlots;
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}
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for (iterator ISJ = begin(); ISJ != end(); ++ISJ)
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DEBUG(dbgs().write_hex(ISJ->Core.getUnits());
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dbgs() << ':'
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<< HexagonMCInstrInfo::getDesc(MCII, *ISJ->getDesc())
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.getOpcode();
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dbgs() << '\n');
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DEBUG(dbgs() << '\n');
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|
return (!getError());
|
|
}
|