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324 lines
9.2 KiB
324 lines
9.2 KiB
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
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; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda -nvvm-intr-range \
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; RUN: | FileCheck --check-prefix=RANGE --check-prefix=RANGE_20 %s
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; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda \
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; RUN: -nvvm-intr-range -nvvm-intr-range-sm=30 \
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; RUN: | FileCheck --check-prefix=RANGE --check-prefix=RANGE_30 %s
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define ptx_device i32 @test_tid_x() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %tid.x;
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; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range ![[BLK_IDX_XY:[0-9]+]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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ret i32 %x
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}
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define ptx_device i32 @test_tid_y() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %tid.y;
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; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.y(), !range ![[BLK_IDX_XY]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
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ret i32 %x
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}
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define ptx_device i32 @test_tid_z() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %tid.z;
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; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.z(), !range ![[BLK_IDX_Z:[0-9]+]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
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ret i32 %x
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}
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define ptx_device i32 @test_tid_w() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %tid.w;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.tid.w()
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ret i32 %x
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}
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define ptx_device i32 @test_ntid_x() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.x;
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; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.x(), !range ![[BLK_SIZE_XY:[0-9]+]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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ret i32 %x
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}
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define ptx_device i32 @test_ntid_y() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.y;
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; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.y(), !range ![[BLK_SIZE_XY]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.y()
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ret i32 %x
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}
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define ptx_device i32 @test_ntid_z() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.z;
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; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.z(), !range ![[BLK_SIZE_Z:[0-9]+]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.z()
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ret i32 %x
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}
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define ptx_device i32 @test_ntid_w() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.w;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.w()
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ret i32 %x
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}
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define ptx_device i32 @test_laneid() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %laneid;
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; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.laneid(), !range ![[LANEID:[0-9]+]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.laneid()
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ret i32 %x
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}
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define ptx_device i32 @test_warpsize() {
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; CHECK: mov.u32 %r{{[0-9]+}}, WARP_SZ;
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; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.warpsize(), !range ![[WARPSIZE:[0-9]+]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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ret i32 %x
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}
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define ptx_device i32 @test_warpid() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %warpid;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.warpid()
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ret i32 %x
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}
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define ptx_device i32 @test_nwarpid() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %nwarpid;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.nwarpid()
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ret i32 %x
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}
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define ptx_device i32 @test_ctaid_y() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.y;
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; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ctaid.y(), !range ![[GRID_IDX_YZ:[0-9]+]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.ctaid.y()
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ret i32 %x
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}
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define ptx_device i32 @test_ctaid_z() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.z;
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; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ctaid.z(), !range ![[GRID_IDX_YZ]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.ctaid.z()
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ret i32 %x
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}
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define ptx_device i32 @test_ctaid_x() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.x;
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; RANGE_30: call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !range ![[GRID_IDX_X:[0-9]+]]
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; RANGE_20: call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !range ![[GRID_IDX_YZ]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
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ret i32 %x
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}
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define ptx_device i32 @test_ctaid_w() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.w;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.ctaid.w()
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ret i32 %x
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}
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define ptx_device i32 @test_nctaid_y() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.y;
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; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.nctaid.y(), !range ![[GRID_SIZE_YZ:[0-9]+]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.nctaid.y()
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ret i32 %x
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}
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define ptx_device i32 @test_nctaid_z() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.z;
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; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.nctaid.z(), !range ![[GRID_SIZE_YZ]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.nctaid.z()
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ret i32 %x
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}
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define ptx_device i32 @test_nctaid_x() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.x;
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; RANGE_30: call i32 @llvm.nvvm.read.ptx.sreg.nctaid.x(), !range ![[GRID_SIZE_X:[0-9]+]]
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; RANGE_20: call i32 @llvm.nvvm.read.ptx.sreg.nctaid.x(), !range ![[GRID_SIZE_YZ]]
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.nctaid.x()
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ret i32 %x
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}
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define ptx_device i32 @test_nctaid_w() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.w;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.nctaid.w()
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ret i32 %x
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}
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define ptx_device i32 @test_smid() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %smid;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.smid()
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ret i32 %x
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}
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define ptx_device i32 @test_nsmid() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %nsmid;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.nsmid()
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ret i32 %x
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}
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define ptx_device i32 @test_gridid() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %gridid;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.gridid()
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ret i32 %x
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}
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define ptx_device i32 @test_lanemask_eq() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %lanemask_eq;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.lanemask.eq()
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ret i32 %x
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}
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define ptx_device i32 @test_lanemask_le() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %lanemask_le;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.lanemask.le()
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ret i32 %x
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}
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define ptx_device i32 @test_lanemask_lt() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %lanemask_lt;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.lanemask.lt()
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ret i32 %x
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}
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define ptx_device i32 @test_lanemask_ge() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %lanemask_ge;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.lanemask.ge()
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ret i32 %x
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}
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define ptx_device i32 @test_lanemask_gt() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %lanemask_gt;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.lanemask.gt()
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ret i32 %x
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}
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define ptx_device i32 @test_clock() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %clock;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.clock()
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ret i32 %x
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}
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define ptx_device i64 @test_clock64() {
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; CHECK: mov.u64 %rd{{[0-9]+}}, %clock64;
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; CHECK: ret;
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%x = call i64 @llvm.nvvm.read.ptx.sreg.clock64()
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ret i64 %x
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}
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define ptx_device i32 @test_pm0() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %pm0;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.pm0()
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ret i32 %x
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}
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define ptx_device i32 @test_pm1() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %pm1;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.pm1()
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ret i32 %x
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}
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define ptx_device i32 @test_pm2() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %pm2;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.pm2()
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ret i32 %x
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}
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define ptx_device i32 @test_pm3() {
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; CHECK: mov.u32 %r{{[0-9]+}}, %pm3;
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; CHECK: ret;
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%x = call i32 @llvm.nvvm.read.ptx.sreg.pm3()
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ret i32 %x
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}
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define ptx_device void @test_bar_sync() {
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; CHECK: bar.sync 0
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; CHECK: ret;
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call void @llvm.nvvm.bar.sync(i32 0)
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ret void
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}
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.w()
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declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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declare i32 @llvm.nvvm.read.ptx.sreg.ntid.y()
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declare i32 @llvm.nvvm.read.ptx.sreg.ntid.z()
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declare i32 @llvm.nvvm.read.ptx.sreg.ntid.w()
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declare i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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declare i32 @llvm.nvvm.read.ptx.sreg.laneid()
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declare i32 @llvm.nvvm.read.ptx.sreg.warpid()
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declare i32 @llvm.nvvm.read.ptx.sreg.nwarpid()
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declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
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declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.y()
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declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.z()
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declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.w()
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declare i32 @llvm.nvvm.read.ptx.sreg.nctaid.x()
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declare i32 @llvm.nvvm.read.ptx.sreg.nctaid.y()
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declare i32 @llvm.nvvm.read.ptx.sreg.nctaid.z()
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declare i32 @llvm.nvvm.read.ptx.sreg.nctaid.w()
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declare i32 @llvm.nvvm.read.ptx.sreg.smid()
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declare i32 @llvm.nvvm.read.ptx.sreg.nsmid()
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declare i32 @llvm.nvvm.read.ptx.sreg.gridid()
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declare i32 @llvm.nvvm.read.ptx.sreg.lanemask.eq()
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declare i32 @llvm.nvvm.read.ptx.sreg.lanemask.le()
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declare i32 @llvm.nvvm.read.ptx.sreg.lanemask.lt()
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declare i32 @llvm.nvvm.read.ptx.sreg.lanemask.ge()
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declare i32 @llvm.nvvm.read.ptx.sreg.lanemask.gt()
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declare i32 @llvm.nvvm.read.ptx.sreg.clock()
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declare i64 @llvm.nvvm.read.ptx.sreg.clock64()
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declare i32 @llvm.nvvm.read.ptx.sreg.pm0()
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declare i32 @llvm.nvvm.read.ptx.sreg.pm1()
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declare i32 @llvm.nvvm.read.ptx.sreg.pm2()
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declare i32 @llvm.nvvm.read.ptx.sreg.pm3()
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declare void @llvm.nvvm.bar.sync(i32 %i)
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; RANGE-DAG: ![[BLK_IDX_XY]] = !{i32 0, i32 1024}
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; RANGE-DAG: ![[BLK_IDX_Z]] = !{i32 0, i32 64}
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; RANGE-DAG: ![[BLK_SIZE_XY]] = !{i32 1, i32 1025}
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; RANGE-DAG: ![[BLK_SIZE_Z]] = !{i32 1, i32 65}
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; RANGE-DAG: ![[LANEID]] = !{i32 0, i32 32}
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; RANGE-DAG: ![[WARPSIZE]] = !{i32 32, i32 33}
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; RANGE_30-DAG: ![[GRID_IDX_X]] = !{i32 0, i32 2147483647}
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; RANGE-DAG: ![[GRID_IDX_YZ]] = !{i32 0, i32 65535}
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; RANGE_30-DAG: ![[GRID_SIZE_X]] = !{i32 1, i32 -2147483648}
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; RANGE-DAG: ![[GRID_SIZE_YZ]] = !{i32 1, i32 65536}
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