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194 lines
6.4 KiB
194 lines
6.4 KiB
// Copyright 2014, VIXL authors
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#include "custom-disassembler.h"
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#include "examples.h"
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using namespace vixl;
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using namespace vixl::aarch64;
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#define __ masm->
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// We override this method to specify how register names should be disassembled.
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void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr,
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const CPURegister& reg) {
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USE(instr);
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if (reg.IsRegister()) {
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switch (reg.GetCode()) {
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case 16:
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AppendToOutput(reg.Is64Bits() ? "ip0" : "wip0");
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return;
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case 17:
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AppendToOutput(reg.Is64Bits() ? "ip1" : "wip1");
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return;
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case 30:
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AppendToOutput(reg.Is64Bits() ? "lr" : "w30");
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return;
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case kSPRegInternalCode:
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AppendToOutput(reg.Is64Bits() ? "x_stack_pointer" : "w_stack_pointer");
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return;
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case 31:
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AppendToOutput(reg.Is64Bits() ? "x_zero_reg" : "w_zero_reg");
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return;
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default:
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// Fall through.
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break;
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}
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}
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// Print other register names as usual.
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Disassembler::AppendRegisterNameToOutput(instr, reg);
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}
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static const char* FakeLookupTargetDescription(const void* address) {
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USE(address);
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// We fake looking up the address.
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static int i = 0;
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const char* desc = NULL;
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if (i == 0) {
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desc = "label: somewhere";
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} else if (i == 2) {
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desc = "label: somewhere else";
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}
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i++;
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return desc;
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}
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// We override this method to add a description to addresses that we know about.
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// In this example we fake looking up a description, but in practice one could
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// for example use a table mapping addresses to function names.
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void CustomDisassembler::AppendCodeRelativeCodeAddressToOutput(
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const Instruction* instr, const void* addr) {
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USE(instr);
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// Print the address.
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int64_t rel_addr = CodeRelativeAddress(addr);
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if (rel_addr >= 0) {
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AppendToOutput("(addr 0x%" PRIx64, rel_addr);
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} else {
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AppendToOutput("(addr -0x%" PRIx64, -rel_addr);
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}
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// If available, print a description of the address.
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const char* address_desc = FakeLookupTargetDescription(addr);
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if (address_desc != NULL) {
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Disassembler::AppendToOutput(" ; %s", address_desc);
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}
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AppendToOutput(")");
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}
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// We override this method to add a comment to this type of instruction. Helpers
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// from the vixl::Instruction class can be used to analyse the instruction being
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// disasssembled.
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void CustomDisassembler::VisitAddSubShifted(const Instruction* instr) {
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vixl::aarch64::Disassembler::VisitAddSubShifted(instr);
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if (instr->GetRd() == 10) {
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AppendToOutput(" // add/sub to x10");
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}
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ProcessOutput(instr);
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}
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void GenerateCustomDisassemblerTestCode(MacroAssembler* masm) {
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// Generate some code to illustrate how the modified disassembler changes the
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// disassembly output.
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Label begin, end;
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__ Bind(&begin);
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__ Add(x10, x16, x17);
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__ Cbz(x10, &end);
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__ Add(x11, ip0, ip1);
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__ Add(w5, w6, w30);
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__ Tbz(x10, 2, &begin);
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__ Tbnz(x10, 3, &begin);
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__ Br(x30);
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__ Br(lr);
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__ Fadd(d30, d16, d17);
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__ Push(xzr, xzr);
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__ Pop(x16, x20);
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__ Bind(&end);
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}
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void TestCustomDisassembler() {
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MacroAssembler masm;
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// Generate the code.
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Label code_start, code_end;
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masm.Bind(&code_start);
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GenerateCustomDisassemblerTestCode(&masm);
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masm.Bind(&code_end);
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masm.FinalizeCode();
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Instruction* instr_start = masm.GetLabelAddress<Instruction*>(&code_start);
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Instruction* instr_end = masm.GetLabelAddress<Instruction*>(&code_end);
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// Instantiate a standard disassembler, our custom disassembler, and register
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// them with a decoder.
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Decoder decoder;
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Disassembler disasm;
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CustomDisassembler custom_disasm;
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decoder.AppendVisitor(&disasm);
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decoder.AppendVisitor(&custom_disasm);
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// In our custom disassembler, disassemble as if the base address was -0x8.
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// Note that this can also be achieved with
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// custom_disasm.MapCodeAddress(0x0, instr_start + 2 * kInstructionSize);
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// Users may generally want to map the start address to 0x0. Mapping to a
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// negative offset can be used to focus on the section of the
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// disassembly at address 0x0.
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custom_disasm.MapCodeAddress(-0x8, instr_start);
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// Iterate through the instructions to show the difference in the disassembly.
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Instruction* instr;
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for (instr = instr_start; instr < instr_end; instr += kInstructionSize) {
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decoder.Decode(instr);
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printf("\n");
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printf("VIXL disasm\t %p:\t%s\n",
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reinterpret_cast<void*>(instr),
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disasm.GetOutput());
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int64_t rel_addr =
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custom_disasm.CodeRelativeAddress(reinterpret_cast<void*>(instr));
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char rel_addr_sign_char = ' ';
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if (rel_addr < 0) {
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rel_addr_sign_char = '-';
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rel_addr = -rel_addr;
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}
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printf("custom disasm\t%c0x%" PRIx64 ":\t%s\n",
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rel_addr_sign_char,
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rel_addr,
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custom_disasm.GetOutput());
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}
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}
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#ifndef TEST_EXAMPLES
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int main() {
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TestCustomDisassembler();
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return 0;
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}
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#endif
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