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v811_spc009/external/vixl/test/aarch64/traces/sim-fjcvtzs-wd-trace-aarch64.h

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// Copyright 2015, VIXL authors
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// * Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
// * Neither the name of ARM Limited nor the names of its contributors may be
// used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ---------------------------------------------------------------------
// This file is auto generated using tools/generate_simulator_traces.py.
//
// PLEASE DO NOT EDIT.
// ---------------------------------------------------------------------
#ifndef VIXL_SIM_FJCVTZS_WD_TRACE_AARCH64_H_
#define VIXL_SIM_FJCVTZS_WD_TRACE_AARCH64_H_
const int32_t kExpected_fjcvtzs_wd[] = {
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(1),
INT32_C(1),
INT32_C(1),
INT32_C(10),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(10),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(1),
INT32_C(1),
INT32_C(1),
INT32_C(1),
INT32_C(1),
INT32_C(1),
INT32_C(1),
INT32_C(1),
INT32_C(1),
INT32_C(1),
INT32_C(1),
INT32_C(1),
INT32_C(1),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(1),
INT32_C(2),
INT32_C(3),
-INT32_C(1450744509),
-INT32_C(4),
-INT32_C(3),
-INT32_C(2),
-INT32_C(1),
INT32_C(0),
INT32_C(0),
INT32_C(1),
INT32_C(1),
-INT32_C(725372255),
-INT32_C(2),
-INT32_C(2),
-INT32_C(1),
-INT32_C(1),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
-INT32_C(362686128),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
INT32_C(0),
-INT32_C(1),
-INT32_C(2),
-INT32_C(3),
INT32_C(1450744509),
INT32_C(4),
INT32_C(3),
INT32_C(2),
INT32_C(1),
INT32_C(0),
INT32_C(0),
-INT32_C(1),
-INT32_C(1),
INT32_C(725372255),
INT32_C(2),
INT32_C(2),
INT32_C(1),
INT32_C(1),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(0),
INT32_C(362686128),
INT32_C(1),
INT32_C(1),
INT32_C(1),
INT32_C(1),
-INT32_C(2048),
INT32_C(0),
INT32_C(1024),
-INT32_C(1024),
INT32_C(0),
-INT32_C(2048),
INT32_C(0),
INT32_C(2147483647),
INT32_C(2147483647),
-INT32_C(2147483647) - 1,
-INT32_C(2147483647) - 1,
-INT32_C(2147483647) - 1,
-INT32_C(2147483647) - 1,
-INT32_C(2147483647) - 1,
-INT32_C(2147483647) - 1,
-INT32_C(2147483647),
-INT32_C(2147483647),
-INT32_C(2147483647),
-INT32_C(2147483647),
INT32_C(2147483645),
INT32_C(2147483646),
INT32_C(2147483646),
INT32_C(2147483646),
INT32_C(2147483646),
INT32_C(2147483646),
INT32_C(2147483646),
INT32_C(2147483647),
INT32_C(2147483647),
INT32_C(2147483647),
INT32_C(2147483647),
INT32_C(2147483647),
-INT32_C(3),
-INT32_C(2),
-INT32_C(2),
-INT32_C(2),
-INT32_C(2),
-INT32_C(2),
-INT32_C(2),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
-INT32_C(1),
};
const unsigned kExpectedCount_fjcvtzs_wd = 207;
#endif // VIXL_SIM_FJCVTZS_WD_TRACE_AARCH64_H_
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