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249 lines
7.9 KiB
249 lines
7.9 KiB
/*
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* Copyright 2012, The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "bcc/CompilerConfig.h"
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#include "Log.h"
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#include "Properties.h"
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#include "bcc/Config.h"
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#include <llvm/CodeGen/SchedulerRegistry.h>
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#include <llvm/MC/SubtargetFeature.h>
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#include <llvm/Support/Host.h>
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#include <llvm/Support/TargetRegistry.h>
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using namespace bcc;
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#if defined (PROVIDE_X86_CODEGEN) && !defined(__HOST__)
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namespace {
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// Utility function to add feature flags supported by the running CPU.
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// This function is only needed for on-device bcc for x86.
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void AddX86NativeCPUFeatures(std::vector<std::string>* attributes) {
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llvm::StringMap<bool> features;
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if (llvm::sys::getHostCPUFeatures(features)) {
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for (const auto& f : features)
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attributes->push_back((f.second ? '+' : '-') + f.first().str());
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}
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// LLVM generates AVX code that treats a long3 as 256 bits, while
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// RenderScript considers a long3 192 bits (http://b/28879581)
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attributes->push_back("-avx");
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}
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}
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#endif // (PROVIDE_X86_CODEGEN) && !defined(__HOST__)
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CompilerConfig::CompilerConfig(const std::string &pTriple)
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: mTriple(pTriple), mFullPrecision(true), mTarget(nullptr) {
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//===--------------------------------------------------------------------===//
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// Default setting of target options
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//===--------------------------------------------------------------------===//
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// Use soft-float ABI. This only selects the ABI (and is applicable only to
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// ARM targets). Codegen still uses hardware FPU by default. To use software
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// floating point, add 'soft-float' feature to mFeatureString below.
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mTargetOpts.FloatABIType = llvm::FloatABI::Soft;
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//===--------------------------------------------------------------------===//
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// Default setting for code model
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//===--------------------------------------------------------------------===//
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mCodeModel = llvm::CodeModel::Small;
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//===--------------------------------------------------------------------===//
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// Default setting for optimization level (-O2)
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//===--------------------------------------------------------------------===//
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mOptLevel = llvm::CodeGenOpt::Default;
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//===--------------------------------------------------------------------===//
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// Default setting for architecture type
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//===--------------------------------------------------------------------===//
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mArchType = llvm::Triple::UnknownArch;
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initializeTarget();
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initializeArch();
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return;
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}
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bool CompilerConfig::initializeTarget() {
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std::string error;
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mTarget = llvm::TargetRegistry::lookupTarget(mTriple, error);
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if (mTarget != nullptr) {
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return true;
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} else {
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ALOGE("Cannot initialize llvm::Target for given triple '%s'! (%s)",
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mTriple.c_str(), error.c_str());
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return false;
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}
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}
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bool CompilerConfig::initializeArch() {
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if (mTarget != nullptr) {
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mArchType = llvm::Triple::getArchTypeForLLVMName(mTarget->getName());
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} else {
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mArchType = llvm::Triple::UnknownArch;
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return false;
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}
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// Configure each architecture for any necessary additional flags.
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std::vector<std::string> attributes;
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switch (mArchType) {
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#if defined(PROVIDE_ARM_CODEGEN)
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case llvm::Triple::arm: {
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llvm::StringMap<bool> features;
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llvm::sys::getHostCPUFeatures(features);
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#if defined(__HOST__) || defined(ARCH_ARM_HAVE_VFP)
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attributes.push_back("+vfp3");
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#if !defined(__HOST__) && !defined(ARCH_ARM_HAVE_VFP_D32)
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attributes.push_back("+d16");
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#endif // !__HOST__ && !ARCH_ARM_HAVE_VFP_D32
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#endif // __HOST__ || ARCH_ARM_HAVE_VFP
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#if defined(__HOST__) || defined(ARCH_ARM_HAVE_NEON)
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// Only enable NEON on ARM if we have relaxed precision floats.
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if (!mFullPrecision) {
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attributes.push_back("+neon");
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} else {
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#endif // __HOST__ || ARCH_ARM_HAVE_NEON
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attributes.push_back("-neon");
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attributes.push_back("-neonfp");
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#if defined(__HOST__) || defined(ARCH_ARM_HAVE_NEON)
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}
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#endif // __HOST__ || ARCH_ARM_HAVE_NEON
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if (!getProperty("debug.rs.arm-no-hwdiv")) {
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if (features.count("hwdiv-arm") && features["hwdiv-arm"])
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attributes.push_back("+hwdiv-arm");
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if (features.count("hwdiv") && features["hwdiv"])
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attributes.push_back("+hwdiv");
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}
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// Enable fp16 attribute if available in the feature list. This feature
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// will not be added in the host version of bcc or bcc_compat since
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// 'features' would correspond to features in an x86 host.
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if (features.count("fp16") && features["fp16"])
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attributes.push_back("+fp16");
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#if defined(PROVIDE_ARM64_CODEGEN)
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// On AArch64, asimd in /proc/cpuinfo signals the presence of hardware
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// half-precision conversion instructions. getHostCPUFeatures translates
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// this to "neon". If PROVIDE_ARM64_CODEGEN is set, enable "+fp16" for ARM
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// codegen if "neon" is present in features.
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if (features.count("neon") && features["neon"])
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attributes.push_back("+fp16");
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#endif // PROVIDE_ARM64_CODEGEN
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#if defined(TARGET_BUILD)
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if (!getProperty("debug.rs.arm-no-tune-for-cpu")) {
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#ifdef DEFAULT_ARM_CODEGEN
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setCPU(llvm::sys::getHostCPUName());
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#endif
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}
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#endif // TARGET_BUILD
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break;
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}
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#endif // PROVIDE_ARM_CODEGEN
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#if defined(PROVIDE_ARM64_CODEGEN)
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case llvm::Triple::aarch64:
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#if defined(TARGET_BUILD)
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if (!getProperty("debug.rs.arm-no-tune-for-cpu")) {
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#ifdef DEFAULT_ARM64_CODEGEN
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setCPU(llvm::sys::getHostCPUName());
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#endif
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}
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#endif // TARGET_BUILD
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break;
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#endif // PROVIDE_ARM64_CODEGEN
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#if defined (PROVIDE_MIPS_CODEGEN)
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case llvm::Triple::mips:
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case llvm::Triple::mipsel:
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if (!mRelocModel.hasValue()) {
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mRelocModel = llvm::Reloc::Static;
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}
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break;
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#endif // PROVIDE_MIPS_CODEGEN
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#if defined (PROVIDE_MIPS64_CODEGEN)
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case llvm::Triple::mips64:
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case llvm::Triple::mips64el:
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// Default revision for MIPS64 Android is R6.
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setCPU("mips64r6");
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break;
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#endif // PROVIDE_MIPS64_CODEGEN
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#if defined (PROVIDE_X86_CODEGEN)
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case llvm::Triple::x86:
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getTargetOptions().UseInitArray = true;
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#if defined (DEFAULT_X86_CODEGEN) && !defined (__HOST__)
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setCPU(llvm::sys::getHostCPUName());
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AddX86NativeCPUFeatures(&attributes);
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#else
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// generic fallback for 32bit x86 targets
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setCPU("atom");
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#endif // DEFAULT_X86_CODEGEN && !__HOST__
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break;
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#endif // PROVIDE_X86_CODEGEN
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#if defined (PROVIDE_X86_CODEGEN)
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// PROVIDE_X86_CODEGEN is defined for both x86 and x86_64
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case llvm::Triple::x86_64:
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#if defined(DEFAULT_X86_64_CODEGEN) && !defined(__HOST__)
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setCPU(llvm::sys::getHostCPUName());
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AddX86NativeCPUFeatures(&attributes);
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#else
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// generic fallback for 64bit x86 targets
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setCPU("core2");
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#endif
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// x86_64 needs small CodeModel if use PIC_ reloc, or else dlopen failed with TEXTREL.
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if (mRelocModel.hasValue() && mRelocModel.getValue() == llvm::Reloc::PIC_) {
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setCodeModel(llvm::CodeModel::Small);
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} else {
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setCodeModel(llvm::CodeModel::Medium);
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}
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getTargetOptions().UseInitArray = true;
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break;
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#endif // PROVIDE_X86_CODEGEN
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default:
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ALOGE("Unsupported architecture type: %s", mTarget->getName());
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return false;
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}
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setFeatureString(attributes);
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return true;
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}
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void CompilerConfig::setFeatureString(const std::vector<std::string> &pAttrs) {
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llvm::SubtargetFeatures f;
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for (std::vector<std::string>::const_iterator attr_iter = pAttrs.begin(),
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attr_end = pAttrs.end();
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attr_iter != attr_end; attr_iter++) {
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f.AddFeature(*attr_iter);
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}
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mFeatureString = f.getString();
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return;
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}
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