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191 lines
5.5 KiB
191 lines
5.5 KiB
/*
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* Copyright (C) 2010-2019 NXP Semiconductors
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _PHNXPNCIHAL_H_
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#define _PHNXPNCIHAL_H_
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#include <hardware/nfc.h>
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#include <phNxpNciHal_utils.h>
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#include "NxpMfcReader.h"
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#include "NxpNfcCapability.h"
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/********************* Definitions and structures *****************************/
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#define MAX_RETRY_COUNT 5
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#define NCI_MAX_DATA_LEN 300
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#define NCI_POLL_DURATION 500
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#define HAL_NFC_ENABLE_I2C_FRAGMENTATION_EVT 0x07
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#undef P2P_PRIO_LOGIC_HAL_IMP
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#define NCI_VERSION_2_0 0x20
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#define NCI_VERSION_1_1 0x11
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#define NCI_VERSION_1_0 0x10
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#define NCI_VERSION_UNKNOWN 0x00
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typedef void(phNxpNciHal_control_granted_callback_t)();
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/*ROM CODE VERSION FW*/
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#define FW_MOBILE_ROM_VERSION_PN551 0x10
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#define FW_MOBILE_ROM_VERSION_PN553 0x11
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#define FW_MOBILE_ROM_VERSION_PN557 0x12
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/* NCI Data */
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#define NCI_MT_CMD 0x20
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#define NCI_MT_RSP 0x40
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#define NCI_MT_NTF 0x60
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#define CORE_RESET_TRIGGER_TYPE_CORE_RESET_CMD_RECEIVED 0x02
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#define CORE_RESET_TRIGGER_TYPE_POWERED_ON 0x01
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#define NCI_MSG_CORE_RESET 0x00
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#define NCI_MSG_CORE_INIT 0x01
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#define NCI_MT_MASK 0xE0
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#define NCI_OID_MASK 0x3F
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#define NXP_MAX_CONFIG_STRING_LEN 260
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#define NCI_HEADER_SIZE 3
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typedef struct nci_data {
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uint16_t len;
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uint8_t p_data[NCI_MAX_DATA_LEN];
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} nci_data_t;
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typedef enum {
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HAL_STATUS_CLOSE = 0,
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HAL_STATUS_OPEN,
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HAL_STATUS_MIN_OPEN
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} phNxpNci_HalStatus;
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typedef enum {
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GPIO_UNKNOWN = 0x00,
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GPIO_STORE = 0x01,
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GPIO_STORE_DONE = 0x02,
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GPIO_RESTORE = 0x10,
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GPIO_RESTORE_DONE = 0x20,
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GPIO_CLEAR = 0xFF
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} phNxpNciHal_GpioInfoState;
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typedef struct phNxpNciGpioInfo {
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phNxpNciHal_GpioInfoState state;
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uint8_t values[2];
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} phNxpNciGpioInfo_t;
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/* Macros to enable and disable extensions */
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#define HAL_ENABLE_EXT() (nxpncihal_ctrl.hal_ext_enabled = 1)
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#define HAL_DISABLE_EXT() (nxpncihal_ctrl.hal_ext_enabled = 0)
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typedef struct phNxpNciInfo {
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uint8_t nci_version;
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bool_t wait_for_ntf;
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} phNxpNciInfo_t;
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/* NCI Control structure */
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typedef struct phNxpNciHal_Control {
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phNxpNci_HalStatus halStatus; /* Indicate if hal is open or closed */
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pthread_t client_thread; /* Integration thread handle */
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uint8_t thread_running; /* Thread running if set to 1, else set to 0 */
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phLibNfc_sConfig_t gDrvCfg; /* Driver config data */
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/* Rx data */
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uint8_t* p_rx_data;
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uint16_t rx_data_len;
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/* Rx data */
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uint8_t* p_rx_ese_data;
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uint16_t rx_ese_data_len;
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/* libnfc-nci callbacks */
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nfc_stack_callback_t* p_nfc_stack_cback;
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nfc_stack_data_callback_t* p_nfc_stack_data_cback;
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/* control granted callback */
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phNxpNciHal_control_granted_callback_t* p_control_granted_cback;
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/* HAL open status */
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bool_t hal_open_status;
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/* HAL extensions */
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uint8_t hal_ext_enabled;
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/* Waiting semaphore */
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phNxpNciHal_Sem_t ext_cb_data;
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sem_t syncSpiNfc;
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uint16_t cmd_len;
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uint8_t p_cmd_data[NCI_MAX_DATA_LEN];
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uint16_t rsp_len;
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uint8_t p_rsp_data[NCI_MAX_DATA_LEN];
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/* retry count used to force download */
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uint16_t retry_cnt;
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uint8_t read_retry_cnt;
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phNxpNciInfo_t nci_info;
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/* to store and restore gpio values */
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phNxpNciGpioInfo_t phNxpNciGpioInfo;
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} phNxpNciHal_Control_t;
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typedef struct phNxpNciClock {
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bool_t isClockSet;
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uint8_t p_rx_data[20];
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bool_t issetConfig;
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} phNxpNciClock_t;
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typedef struct phNxpNciRfSetting {
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bool_t isGetRfSetting;
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uint8_t p_rx_data[20];
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} phNxpNciRfSetting_t;
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typedef struct phNxpNciMwEepromArea {
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bool_t isGetEepromArea;
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uint8_t p_rx_data[32];
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} phNxpNciMwEepromArea_t;
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typedef enum {
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NFC_FORUM_PROFILE,
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EMV_CO_PROFILE,
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INVALID_PROFILe
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} phNxpNciProfile_t;
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/* NXP Poll Profile control structure */
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typedef struct phNxpNciProfile_Control {
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phNxpNciProfile_t profile_type;
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uint8_t bClkSrcVal; /* Holds the System clock source read from config file */
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uint8_t
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bClkFreqVal; /* Holds the System clock frequency read from config file */
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uint8_t bTimeout; /* Holds the Timeout Value */
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} phNxpNciProfile_Control_t;
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/* Internal messages to handle callbacks */
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#define NCI_HAL_OPEN_CPLT_MSG 0x411
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#define NCI_HAL_CLOSE_CPLT_MSG 0x412
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#define NCI_HAL_POST_INIT_CPLT_MSG 0x413
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#define NCI_HAL_PRE_DISCOVER_CPLT_MSG 0x414
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#define NCI_HAL_ERROR_MSG 0x415
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#define NCI_HAL_HCI_NETWORK_RESET_MSG 0x416
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#define NCI_HAL_RX_MSG 0xF01
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#define NCIHAL_CMD_CODE_LEN_BYTE_OFFSET (2U)
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#define NCIHAL_CMD_CODE_BYTE_LEN (3U)
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/******************** NCI HAL exposed functions *******************************/
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int phNxpNciHal_check_ncicmd_write_window(uint16_t cmd_len, uint8_t* p_cmd);
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void phNxpNciHal_request_control(void);
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void phNxpNciHal_release_control(void);
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int phNxpNciHal_write_unlocked(uint16_t data_len, const uint8_t* p_data);
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/*******************************************************************************
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**
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** Function phNxpNciHal_configFeatureList
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**
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** Description Configures the featureList based on chip type
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** Returns none
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*******************************************************************************/
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void phNxpNciHal_configFeatureList(uint8_t* init_rsp, uint16_t rsp_len);
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#endif /* _PHNXPNCIHAL_H_ */
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