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616 lines
20 KiB
616 lines
20 KiB
/*
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* Copyright (c) Hisilicon Technologies Co., Ltd.. 2021-2021. All rights reserved.
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* Description: pwm driver for reserved5/reserved2 chip.
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* Author:
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* Create: 2021-05-12
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* Note:
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*/
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/********************************************************************************************/
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/* Includes */
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/********************************************************************************************/
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#include "osal_ext.h"
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#include "pwm_common.h"
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#include "pwm_v2.h"
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/********************************************************************************************/
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/* Structure */
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/********************************************************************************************/
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typedef union {
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struct {
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td_u32 reserved : 4;
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td_u32 period : 28;
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} bits;
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td_u32 u32;
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} _gpio_pwm_cfg_v2;
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typedef union {
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struct {
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td_u32 enable : 1;
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td_u32 inv : 1;
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td_u32 reserved : 2;
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td_u32 duty : 28;
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} bits;
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td_u32 u32;
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} _gpio_pwm_ctrl_v2;
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typedef union {
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struct {
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td_u32 period : 28;
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td_u32 reserved : 4;
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} bits;
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td_u32 u32;
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} _gpio_pwm_state0_v2;
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typedef union {
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struct {
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td_u32 duty : 28;
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td_u32 reserved : 4;
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} bits;
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td_u32 u32;
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} _gpio_pwm_state1_v2;
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typedef union {
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struct {
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td_u32 reserved : 4;
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td_u32 period : 28;
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} bits;
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td_u32 u32;
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} _led_pwm_cfg_v2;
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typedef union {
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struct {
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td_u32 enable : 1;
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td_u32 inv : 1;
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td_u32 reserved : 2;
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td_u32 duty : 28;
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} bits;
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td_u32 u32;
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} _led_pwm_ctrl_v2;
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typedef union {
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struct {
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td_u32 period : 28;
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td_u32 reserved : 4;
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} bits;
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td_u32 u32;
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} _led_pwm_state0_v2;
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typedef union {
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struct {
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td_u32 duty : 28;
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td_u32 reserved : 4;
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} bits;
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td_u32 u32;
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} _led_pwm_state1_v2;
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/*
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pwm num : 4 (下电区)
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led_pwm num : 1 (常电区)
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*/
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typedef struct { /* pwm: 4, led_pwm: 1 */
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td_u32 pwm_phy_addr; /* 0xF8B30000 */
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td_u32 pwm_addr_space_size; /* 0x1000 */
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volatile td_void *pwm_base_addr;
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td_u32 pwm_clk_freq; /* 54MHz */
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td_u16 pwm_base_addr_offset; /* 0x20 */
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td_u16 pwm_num; /* 4 */
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td_u16 pwm_bit_num; /* 8 */
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td_u32 led_pwm_phy_addr; /* 0xF800A000 */
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td_u32 led_pwm_addr_space_size; /* 0x1000 */
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volatile td_void *led_pwm_base_addr;
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td_u32 led_pwm_clk_freq; /* 24MHz */
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td_u16 led_pwm_num; /* 1 */
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td_u16 bri_pwm_num; /* 4 */
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td_u32 pwm_freq_critical; /* 10Hz */
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td_u16 offset_cfg; /* 0x0 */
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td_u16 offset_ctrl; /* 0x4 */
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td_u16 offset_state0_period; /* 0x8 */
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td_u16 offset_state1_duty; /* 0xC */
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} pwm_info_v2;
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/********************************************************************************************/
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/* Globals */
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/********************************************************************************************/
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static pwm_info_v2 g_pwm_info_v2 = {0};
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/********************************************************************************************
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Function Implementation
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********************************************************************************************/
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static td_s32 _pwm_get_gpio_pwm_reg_addr_v2(td_void)
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{
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td_s32 ret = TD_SUCCESS;
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pwm_info_v2 *v2 = &g_pwm_info_v2;
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v2->pwm_base_addr = osal_ioremap_nocache(v2->pwm_phy_addr, v2->pwm_addr_space_size);
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pwm_check_param(ret, TD_FAILURE, v2->pwm_base_addr == TD_NULL, goto out);
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out:
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return ret;
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}
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static td_s32 _pwm_get_led_pwm_reg_addr_v2(td_void)
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{
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td_s32 ret = TD_SUCCESS;
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pwm_info_v2 *v2 = &g_pwm_info_v2;
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v2->led_pwm_base_addr = osal_ioremap_nocache(v2->led_pwm_phy_addr, v2->led_pwm_addr_space_size);
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pwm_check_param(ret, TD_FAILURE, v2->led_pwm_base_addr == TD_NULL, goto out);
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out:
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return ret;
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}
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static td_s32 _pwm_get_regs_v2(td_u32 pwm_no, pwm_reg_s *reg)
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{
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td_s32 ret = TD_SUCCESS;
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const pwm_info_v2 *v2 = &g_pwm_info_v2;
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pwm_check_param(ret, TD_FAILURE, reg == TD_NULL, goto out);
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if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
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reg->cfg = (uintptr_t)(v2->pwm_base_addr + v2->pwm_base_addr_offset * pwm_no + v2->offset_cfg);
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reg->ctrl = (uintptr_t)(v2->pwm_base_addr + v2->pwm_base_addr_offset * pwm_no + v2->offset_ctrl);
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reg->state0 = (uintptr_t)(v2->pwm_base_addr + v2->pwm_base_addr_offset * pwm_no + v2->offset_state0_period);
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reg->state1 = (uintptr_t)(v2->pwm_base_addr + v2->pwm_base_addr_offset * pwm_no + v2->offset_state1_duty);
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} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
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reg->cfg = (uintptr_t)(v2->led_pwm_base_addr + v2->offset_cfg);
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reg->ctrl = (uintptr_t)(v2->led_pwm_base_addr + v2->offset_ctrl);
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reg->state0 = (uintptr_t)(v2->led_pwm_base_addr + v2->offset_state0_period);
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reg->state1 = (uintptr_t)(v2->led_pwm_base_addr + v2->offset_state1_duty);
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} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
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soc_log_info("bri pwm is not implemented currently!\n");
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ret = TD_SUCCESS;
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goto out;
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} else {
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soc_log_err("[get_regs] Invalid pwm_no %u for v2! The range is 0~%u\n",
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pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
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ret = TD_FAILURE;
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goto out;
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}
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out:
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return ret;
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}
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static td_s32 _pwm_get_freq_v2(td_u32 pwm_no, td_u32 *freq)
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{
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td_s32 ret = TD_SUCCESS;
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pwm_info_v2 *v2 = &g_pwm_info_v2;
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pwm_check_param(ret, TD_FAILURE, freq == TD_NULL, goto out);
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if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
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*freq = v2->pwm_clk_freq; /* 54MHz */
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} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
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*freq = v2->led_pwm_clk_freq; /* 24MHz */
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} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
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soc_log_info("bri pwm is not implemented currently!\n");
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ret = TD_SUCCESS;
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goto out;
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} else {
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soc_log_err("[get_freq] Invalid pwm_no %u for v2! The range is 0~%u\n",
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pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
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ret = TD_FAILURE;
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goto out;
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}
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out:
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return ret;
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}
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static td_s32 _gpio_pwm_get_state_v2(td_u32 pwm_no, ext_drv_pwm_attr *pwm_attr)
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{
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td_s32 ret;
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pwm_reg_s reg = {0};
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td_u32 freq;
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_gpio_pwm_state0_v2 state0;
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_gpio_pwm_state1_v2 state1;
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_gpio_pwm_ctrl_v2 ctrl;
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pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);
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pwm_func_call(ret, _pwm_get_freq_v2(pwm_no, &freq), goto out);
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pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, ®), goto out);
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state0.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.state0);
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state1.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.state1);
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ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);
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pwm_func_call(ret, pwm_get_attr(freq, state0.bits.period, state1.bits.duty, ctrl.bits.inv, pwm_attr), goto out);
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out:
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return ret;
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}
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static td_s32 _led_pwm_get_state_v2(td_u32 pwm_no, ext_drv_pwm_attr *pwm_attr)
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{
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td_s32 ret;
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pwm_reg_s reg = {0};
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td_u32 freq;
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_led_pwm_state0_v2 state0;
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_led_pwm_state1_v2 state1;
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_led_pwm_ctrl_v2 ctrl;
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pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);
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pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, ®), goto out);
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pwm_func_call(ret, _pwm_get_freq_v2(pwm_no, &freq), goto out);
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state0.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.state0);
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state1.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.state1);
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ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);
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pwm_func_call(ret, pwm_get_attr(freq, state0.bits.period, state1.bits.duty, ctrl.bits.inv, pwm_attr), goto out);
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out:
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return ret;
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}
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static td_s32 _gpio_pwm_get_attr_v2(td_u32 pwm_no, ext_drv_pwm_attr *pwm_attr)
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{
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td_s32 ret;
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pwm_reg_s reg = {0};
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td_u32 freq;
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_gpio_pwm_cfg_v2 cfg;
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_gpio_pwm_ctrl_v2 ctrl;
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pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);
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pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, ®), goto out);
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pwm_func_call(ret, _pwm_get_freq_v2(pwm_no, &freq), goto out);
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cfg.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.cfg);
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ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);
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pwm_func_call(ret, pwm_get_attr(freq, cfg.bits.period, ctrl.bits.duty, ctrl.bits.inv, pwm_attr), goto out);
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out:
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return ret;
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}
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static td_s32 _led_pwm_get_attr_v2(td_u32 pwm_no, ext_drv_pwm_attr *pwm_attr)
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{
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td_s32 ret;
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pwm_reg_s reg = {0};
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td_u32 freq;
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_led_pwm_cfg_v2 cfg;
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_led_pwm_ctrl_v2 ctrl;
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pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);
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pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, ®), goto out);
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pwm_func_call(ret, _pwm_get_freq_v2(pwm_no, &freq), goto out);
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cfg.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.cfg);
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ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);
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pwm_func_call(ret, pwm_get_attr(freq, cfg.bits.period, ctrl.bits.duty, ctrl.bits.inv, pwm_attr), goto out);
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out:
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return ret;
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}
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static td_s32 _gpio_pwm_set_attr_v2(td_u32 pwm_no, const ext_drv_pwm_attr *pwm_attr)
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{
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td_s32 ret;
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const pwm_info_v2 *v2 = &g_pwm_info_v2;
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pwm_reg_s reg = {0};
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pwm_info info = {0};
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_gpio_pwm_cfg_v2 cfg = {
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.bits.period = ~0,
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.u32 = ~0
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};
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pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);
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pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, ®), goto out);
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pwm_func_call(ret, _pwm_get_freq_v2(pwm_no, &info.pwm_clk_freq), goto out);
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info.pwm_freq_critical = v2->pwm_freq_critical;
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info.period_duty_offset = pwm_get_bit_count(cfg.u32) - pwm_get_bit_count(cfg.bits.period);
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info.pwm_reg = ®
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info.pwm_attr = pwm_attr;
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pwm_func_call(ret, pwm_set_attr(&info), goto out);
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out:
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return ret;
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}
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static td_s32 _led_pwm_set_attr_v2(td_u32 pwm_no, const ext_drv_pwm_attr *pwm_attr)
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{
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td_s32 ret;
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const pwm_info_v2 *v2 = &g_pwm_info_v2;
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pwm_reg_s reg = {0};
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pwm_info info = {0};
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_led_pwm_cfg_v2 cfg = {
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.bits.period = ~0,
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.u32 = ~0
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};
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pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);
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pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, ®), goto out);
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pwm_func_call(ret, _pwm_get_freq_v2(pwm_no, &info.pwm_clk_freq), goto out);
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info.pwm_freq_critical = v2->pwm_freq_critical;
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info.period_duty_offset = pwm_get_bit_count(cfg.u32) - pwm_get_bit_count(cfg.bits.period);
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info.pwm_attr = pwm_attr;
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info.pwm_reg = ®
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pwm_func_call(ret, pwm_set_attr(&info), goto out);
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out:
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return ret;
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}
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static td_s32 _gpio_pwm_set_enable_v2(td_u32 pwm_no, td_bool enable)
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{
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td_s32 ret;
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pwm_reg_s reg = {0};
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_gpio_pwm_ctrl_v2 ctrl;
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pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, ®), goto out);
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ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);
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ctrl.bits.enable = enable;
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osal_writel(ctrl.u32, (td_void *)(uintptr_t)reg.ctrl);
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out:
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return ret;
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}
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static td_s32 _led_pwm_set_enable_v2(td_u32 pwm_no, td_bool enable)
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{
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td_s32 ret;
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pwm_reg_s reg = {0};
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_led_pwm_ctrl_v2 ctrl;
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pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, ®), goto out);
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ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);
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ctrl.bits.enable = enable;
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osal_writel(ctrl.u32, (td_void *)(uintptr_t)reg.ctrl);
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out:
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return ret;
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}
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static td_s32 _gpio_pwm_get_enable_v2(td_u32 pwm_no, td_bool *enable)
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{
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td_s32 ret;
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pwm_reg_s reg = {0};
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_gpio_pwm_ctrl_v2 ctrl;
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pwm_check_param(ret, TD_FAILURE, enable == TD_NULL, goto out);
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pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, ®), goto out);
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ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);
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*enable = ctrl.bits.enable;
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out:
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return ret;
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}
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static td_s32 _led_pwm_get_enable_v2(td_u32 pwm_no, td_bool *enable)
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{
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td_s32 ret;
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pwm_reg_s reg = {0};
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_led_pwm_ctrl_v2 ctrl;
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pwm_check_param(ret, TD_FAILURE, enable == TD_NULL, goto out);
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pwm_func_call(ret, _pwm_get_regs_v2(pwm_no, ®), goto out);
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ctrl.u32 = (uintptr_t)osal_readl((td_void *)(uintptr_t)reg.ctrl);
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*enable = ctrl.bits.enable;
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out:
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return ret;
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}
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td_s32 pwm_deinit_v2(td_void)
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{
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pwm_info_v2 *v2 = &g_pwm_info_v2;
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if (v2->pwm_base_addr != TD_NULL) {
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osal_iounmap((td_void *)v2->pwm_base_addr, OSAL_IOUNMAP_SIZE);
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v2->pwm_base_addr = TD_NULL;
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}
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if (v2->led_pwm_base_addr != TD_NULL) {
|
|
osal_iounmap((td_void *)v2->led_pwm_base_addr, OSAL_IOUNMAP_SIZE);
|
|
v2->led_pwm_base_addr = TD_NULL;
|
|
}
|
|
|
|
return TD_SUCCESS;
|
|
}
|
|
|
|
td_s32 pwm_init_v2(td_void)
|
|
{
|
|
td_s32 ret = TD_SUCCESS;
|
|
pwm_info_v2 *v2 = &g_pwm_info_v2;
|
|
|
|
v2->pwm_phy_addr = 0xF8B30000; /* pwm physical addr : 0xF8B30000 */
|
|
v2->pwm_addr_space_size = 0x1000; /* pwm addr space size : 0x1000 */
|
|
pwm_func_call(ret, _pwm_get_gpio_pwm_reg_addr_v2(), goto deinit);
|
|
v2->pwm_clk_freq = 54000000; /* 54000000 MHz */
|
|
v2->pwm_base_addr_offset = 0x20; /* pwm_base_addr_offset : 0x20 */
|
|
v2->pwm_num = 4; /* pwm_num number : 4 */
|
|
v2->pwm_bit_num = 8; /* gpio_pwm_bit_num : 8 */
|
|
|
|
v2->led_pwm_phy_addr = 0xF800A000; /* led pwm physical addr : 0xF800A000 */
|
|
v2->led_pwm_addr_space_size = 0x1000; /* led pwm addr space size : 0x1000 */
|
|
pwm_func_call(ret, _pwm_get_led_pwm_reg_addr_v2(), goto deinit);
|
|
v2->led_pwm_clk_freq = 24000000; /* led_pwm_clk_freq : 24000000 MHz */
|
|
v2->led_pwm_num = 1; /* led_pwm_num : 1 */
|
|
|
|
v2->bri_pwm_num = 4; /* bri_pwm_num : 4 */
|
|
|
|
v2->pwm_freq_critical = 10; /* 10 Hz */
|
|
|
|
v2->offset_cfg = 0x0; /* offset_cfg : 0x0 */
|
|
v2->offset_ctrl = 0x4; /* offset_ctrl : 0x4 */
|
|
v2->offset_state0_period = 0x8; /* offset_state0_period : 0x8 */
|
|
v2->offset_state1_duty = 0xC; /* offset_state1_duty : 0xC */
|
|
|
|
goto out;
|
|
|
|
deinit:
|
|
pwm_func_call(ret, pwm_deinit_v2(), goto out);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
td_s32 pwm_get_state_v2(td_u32 pwm_no, ext_drv_pwm_attr *pwm_attr)
|
|
{
|
|
td_s32 ret;
|
|
const pwm_info_v2 *v2 = &g_pwm_info_v2;
|
|
|
|
pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);
|
|
|
|
if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
|
|
pwm_func_call(ret, _gpio_pwm_get_state_v2(pwm_no, pwm_attr), goto out);
|
|
} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
|
|
pwm_func_call(ret, _led_pwm_get_state_v2(pwm_no, pwm_attr), goto out);
|
|
} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
|
|
soc_log_info("bri pwm is not implemented currently!\n");
|
|
ret = TD_SUCCESS;
|
|
goto out;
|
|
} else {
|
|
soc_log_err("[get_state] Invalid pwm_no %u for v2! The range is 0~%u\n",
|
|
pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
|
|
ret = TD_FAILURE;
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
td_s32 pwm_get_attr_v2(td_u32 pwm_no, ext_drv_pwm_attr *pwm_attr)
|
|
{
|
|
td_s32 ret;
|
|
const pwm_info_v2 *v2 = &g_pwm_info_v2;
|
|
|
|
pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);
|
|
|
|
if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
|
|
pwm_func_call(ret, _gpio_pwm_get_attr_v2(pwm_no, pwm_attr), goto out);
|
|
} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
|
|
pwm_func_call(ret, _led_pwm_get_attr_v2(pwm_no, pwm_attr), goto out);
|
|
} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
|
|
soc_log_info("bri pwm is not implemented currently!\n");
|
|
ret = TD_SUCCESS;
|
|
goto out;
|
|
} else {
|
|
soc_log_err("[get_attr] Invalid pwm_no %u for v2! The range is 0~%u\n",
|
|
pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
|
|
ret = TD_FAILURE;
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
td_s32 pwm_set_attr_v2(td_u32 pwm_no, const ext_drv_pwm_attr *pwm_attr)
|
|
{
|
|
td_s32 ret;
|
|
const pwm_info_v2 *v2 = &g_pwm_info_v2;
|
|
|
|
pwm_check_param(ret, TD_FAILURE, pwm_attr == TD_NULL, goto out);
|
|
|
|
if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
|
|
pwm_func_call(ret, _gpio_pwm_set_attr_v2(pwm_no, pwm_attr), goto out);
|
|
} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
|
|
pwm_func_call(ret, _led_pwm_set_attr_v2(pwm_no, pwm_attr), goto out);
|
|
} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
|
|
soc_log_info("bri pwm is not implemented currently!\n");
|
|
ret = TD_SUCCESS;
|
|
goto out;
|
|
} else {
|
|
soc_log_err("[set_attr] Invalid pwm_no %u for v2! The range is 0~%u\n",
|
|
pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
|
|
ret = TD_FAILURE;
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
td_s32 pwm_set_enable_v2(td_u32 pwm_no, td_bool enable)
|
|
{
|
|
td_s32 ret;
|
|
const pwm_info_v2 *v2 = &g_pwm_info_v2;
|
|
|
|
if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
|
|
pwm_func_call(ret, _gpio_pwm_set_enable_v2(pwm_no, enable), goto out);
|
|
} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
|
|
pwm_func_call(ret, _led_pwm_set_enable_v2(pwm_no, enable), goto out);
|
|
} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
|
|
soc_log_info("bri pwm is not implemented currently!\n");
|
|
ret = TD_SUCCESS;
|
|
goto out;
|
|
} else {
|
|
soc_log_err("[set_enable] Invalid pwm_no %u for v2! The range is 0~%u\n",
|
|
pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
|
|
ret = TD_FAILURE;
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
td_s32 pwm_get_enable_v2(td_u32 pwm_no, td_bool *enable)
|
|
{
|
|
td_s32 ret;
|
|
const pwm_info_v2 *v2 = &g_pwm_info_v2;
|
|
|
|
pwm_check_param(ret, TD_FAILURE, enable == TD_NULL, goto out);
|
|
|
|
if (pwm_no < v2->pwm_num) { /* The pwm_no of pwm is 0~3 */
|
|
pwm_func_call(ret, _gpio_pwm_get_enable_v2(pwm_no, enable), goto out);
|
|
} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num)) { /* The pwm_no of led_pwm is 4 */
|
|
pwm_func_call(ret, _led_pwm_get_enable_v2(pwm_no, enable), goto out);
|
|
} else if (pwm_no < (v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num)) { /* 5,6,7,8 is BRI_PWM0 - BRI_PWM3 */
|
|
soc_log_info("bri pwm is not implemented currently!\n");
|
|
ret = TD_SUCCESS;
|
|
goto out;
|
|
} else {
|
|
soc_log_err("[get_enable] Invalid pwm_no %u for v2! The range is 0~%u\n",
|
|
pwm_no, v2->pwm_num + v2->led_pwm_num + v2->bri_pwm_num - 1);
|
|
ret = TD_FAILURE;
|
|
goto out;
|
|
}
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
td_s32 pwm_send_signal_v2(td_u32 pwm_no, td_u32 carrier_signal_duration_us, td_u32 low_level_signal_duration_us)
|
|
{
|
|
soc_log_info("RESERVED5 chip not support pwm_send_signal!\n");
|
|
|
|
return TD_SUCCESS;
|
|
}
|