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616 lines
24 KiB
616 lines
24 KiB
//===-- FunctionLoweringInfo.cpp ------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements routines for translating functions from LLVM IR into
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// Machine IR.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/WinEHFuncInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DebugInfo.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <algorithm>
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using namespace llvm;
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#define DEBUG_TYPE "function-lowering-info"
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/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
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/// PHI nodes or outside of the basic block that defines it, or used by a
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/// switch or atomic instruction, which may expand to multiple basic blocks.
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static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
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if (I->use_empty()) return false;
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if (isa<PHINode>(I)) return true;
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const BasicBlock *BB = I->getParent();
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for (const User *U : I->users())
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if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
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return true;
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return false;
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}
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static ISD::NodeType getPreferredExtendForValue(const Value *V) {
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// For the users of the source value being used for compare instruction, if
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// the number of signed predicate is greater than unsigned predicate, we
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// prefer to use SIGN_EXTEND.
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//
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// With this optimization, we would be able to reduce some redundant sign or
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// zero extension instruction, and eventually more machine CSE opportunities
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// can be exposed.
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ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
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unsigned NumOfSigned = 0, NumOfUnsigned = 0;
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for (const User *U : V->users()) {
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if (const auto *CI = dyn_cast<CmpInst>(U)) {
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NumOfSigned += CI->isSigned();
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NumOfUnsigned += CI->isUnsigned();
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}
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}
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if (NumOfSigned > NumOfUnsigned)
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ExtendKind = ISD::SIGN_EXTEND;
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return ExtendKind;
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}
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void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
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SelectionDAG *DAG) {
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Fn = &fn;
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MF = &mf;
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TLI = MF->getSubtarget().getTargetLowering();
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RegInfo = &MF->getRegInfo();
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MachineModuleInfo &MMI = MF->getMMI();
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const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
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unsigned StackAlign = TFI->getStackAlignment();
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// Check whether the function can return without sret-demotion.
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SmallVector<ISD::OutputArg, 4> Outs;
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GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
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mf.getDataLayout());
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CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
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Fn->isVarArg(), Outs, Fn->getContext());
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// If this personality uses funclets, we need to do a bit more work.
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DenseMap<const AllocaInst *, int *> CatchObjects;
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EHPersonality Personality = classifyEHPersonality(
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Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr);
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if (isFuncletEHPersonality(Personality)) {
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// Calculate state numbers if we haven't already.
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WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
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if (Personality == EHPersonality::MSVC_CXX)
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calculateWinCXXEHStateNumbers(&fn, EHInfo);
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else if (isAsynchronousEHPersonality(Personality))
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calculateSEHStateNumbers(&fn, EHInfo);
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else if (Personality == EHPersonality::CoreCLR)
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calculateClrEHStateNumbers(&fn, EHInfo);
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// Map all BB references in the WinEH data to MBBs.
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for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
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for (WinEHHandlerType &H : TBME.HandlerArray) {
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if (const AllocaInst *AI = H.CatchObj.Alloca)
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CatchObjects.insert({AI, &H.CatchObj.FrameIndex});
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else
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H.CatchObj.FrameIndex = INT_MAX;
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}
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}
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}
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// Initialize the mapping of values to registers. This is only set up for
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// instruction values that are used outside of the block that defines
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// them.
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Function::const_iterator BB = Fn->begin(), EB = Fn->end();
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for (; BB != EB; ++BB)
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for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
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I != E; ++I) {
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if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
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Type *Ty = AI->getAllocatedType();
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unsigned Align =
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std::max((unsigned)MF->getDataLayout().getPrefTypeAlignment(Ty),
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AI->getAlignment());
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// Static allocas can be folded into the initial stack frame
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// adjustment. For targets that don't realign the stack, don't
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// do this if there is an extra alignment requirement.
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if (AI->isStaticAlloca() &&
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(TFI->isStackRealignable() || (Align <= StackAlign))) {
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const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
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uint64_t TySize = MF->getDataLayout().getTypeAllocSize(Ty);
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TySize *= CUI->getZExtValue(); // Get total allocated size.
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if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
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int FrameIndex = INT_MAX;
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auto Iter = CatchObjects.find(AI);
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if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) {
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FrameIndex = MF->getFrameInfo()->CreateFixedObject(
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TySize, 0, /*Immutable=*/false, /*isAliased=*/true);
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MF->getFrameInfo()->setObjectAlignment(FrameIndex, Align);
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} else {
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FrameIndex =
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MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
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}
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StaticAllocaMap[AI] = FrameIndex;
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// Update the catch handler information.
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if (Iter != CatchObjects.end())
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*Iter->second = FrameIndex;
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} else {
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// FIXME: Overaligned static allocas should be grouped into
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// a single dynamic allocation instead of using a separate
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// stack allocation for each one.
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if (Align <= StackAlign)
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Align = 0;
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// Inform the Frame Information that we have variable-sized objects.
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MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
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}
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}
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// Look for inline asm that clobbers the SP register.
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if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
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ImmutableCallSite CS(&*I);
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if (isa<InlineAsm>(CS.getCalledValue())) {
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unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
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const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
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std::vector<TargetLowering::AsmOperandInfo> Ops =
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TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, CS);
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for (size_t I = 0, E = Ops.size(); I != E; ++I) {
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TargetLowering::AsmOperandInfo &Op = Ops[I];
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if (Op.Type == InlineAsm::isClobber) {
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// Clobbers don't have SDValue operands, hence SDValue().
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TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
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std::pair<unsigned, const TargetRegisterClass *> PhysReg =
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TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
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Op.ConstraintVT);
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if (PhysReg.first == SP)
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MF->getFrameInfo()->setHasOpaqueSPAdjustment(true);
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}
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}
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}
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}
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// Look for calls to the @llvm.va_start intrinsic. We can omit some
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// prologue boilerplate for variadic functions that don't examine their
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// arguments.
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if (const auto *II = dyn_cast<IntrinsicInst>(I)) {
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if (II->getIntrinsicID() == Intrinsic::vastart)
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MF->getFrameInfo()->setHasVAStart(true);
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}
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// If we have a musttail call in a variadic function, we need to ensure we
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// forward implicit register parameters.
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if (const auto *CI = dyn_cast<CallInst>(I)) {
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if (CI->isMustTailCall() && Fn->isVarArg())
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MF->getFrameInfo()->setHasMustTailInVarArgFunc(true);
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}
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// Mark values used outside their block as exported, by allocating
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// a virtual register for them.
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if (isUsedOutsideOfDefiningBlock(&*I))
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if (!isa<AllocaInst>(I) || !StaticAllocaMap.count(cast<AllocaInst>(I)))
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InitializeRegForValue(&*I);
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// Collect llvm.dbg.declare information. This is done now instead of
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// during the initial isel pass through the IR so that it is done
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// in a predictable order.
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if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
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assert(DI->getVariable() && "Missing variable");
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assert(DI->getDebugLoc() && "Missing location");
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if (MMI.hasDebugInfo()) {
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// Don't handle byval struct arguments or VLAs, for example.
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// Non-byval arguments are handled here (they refer to the stack
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// temporary alloca at this point).
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const Value *Address = DI->getAddress();
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if (Address) {
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if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
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Address = BCI->getOperand(0);
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if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
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DenseMap<const AllocaInst *, int>::iterator SI =
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StaticAllocaMap.find(AI);
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if (SI != StaticAllocaMap.end()) { // Check for VLAs.
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int FI = SI->second;
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MMI.setVariableDbgInfo(DI->getVariable(), DI->getExpression(),
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FI, DI->getDebugLoc());
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}
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}
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}
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}
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}
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// Decide the preferred extend type for a value.
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PreferredExtendType[&*I] = getPreferredExtendForValue(&*I);
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}
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// Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
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// also creates the initial PHI MachineInstrs, though none of the input
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// operands are populated.
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for (BB = Fn->begin(); BB != EB; ++BB) {
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// Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks
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// are really data, and no instructions can live here.
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if (BB->isEHPad()) {
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const Instruction *I = BB->getFirstNonPHI();
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// If this is a non-landingpad EH pad, mark this function as using
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// funclets.
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// FIXME: SEH catchpads do not create funclets, so we could avoid setting
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// this in such cases in order to improve frame layout.
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if (!isa<LandingPadInst>(I)) {
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MMI.setHasEHFunclets(true);
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MF->getFrameInfo()->setHasOpaqueSPAdjustment(true);
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}
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if (isa<CatchSwitchInst>(I)) {
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assert(&*BB->begin() == I &&
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"WinEHPrepare failed to remove PHIs from imaginary BBs");
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continue;
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}
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if (isa<FuncletPadInst>(I))
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assert(&*BB->begin() == I && "WinEHPrepare failed to demote PHIs");
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}
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MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&*BB);
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MBBMap[&*BB] = MBB;
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MF->push_back(MBB);
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// Transfer the address-taken flag. This is necessary because there could
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// be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
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// the first one should be marked.
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if (BB->hasAddressTaken())
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MBB->setHasAddressTaken();
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// Create Machine PHI nodes for LLVM PHI nodes, lowering them as
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// appropriate.
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for (BasicBlock::const_iterator I = BB->begin();
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const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
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if (PN->use_empty()) continue;
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// Skip empty types
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if (PN->getType()->isEmptyTy())
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continue;
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DebugLoc DL = PN->getDebugLoc();
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unsigned PHIReg = ValueMap[PN];
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assert(PHIReg && "PHI node does not have an assigned virtual register!");
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(*TLI, MF->getDataLayout(), PN->getType(), ValueVTs);
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for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
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EVT VT = ValueVTs[vti];
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unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
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const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
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for (unsigned i = 0; i != NumRegisters; ++i)
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BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
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PHIReg += NumRegisters;
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}
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}
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}
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// Mark landing pad blocks.
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SmallVector<const LandingPadInst *, 4> LPads;
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for (BB = Fn->begin(); BB != EB; ++BB) {
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const Instruction *FNP = BB->getFirstNonPHI();
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if (BB->isEHPad() && MBBMap.count(&*BB))
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MBBMap[&*BB]->setIsEHPad();
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if (const auto *LPI = dyn_cast<LandingPadInst>(FNP))
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LPads.push_back(LPI);
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}
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if (!isFuncletEHPersonality(Personality))
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return;
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WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
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// Map all BB references in the WinEH data to MBBs.
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for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
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for (WinEHHandlerType &H : TBME.HandlerArray) {
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if (H.Handler)
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H.Handler = MBBMap[H.Handler.get<const BasicBlock *>()];
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}
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}
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for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap)
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if (UME.Cleanup)
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UME.Cleanup = MBBMap[UME.Cleanup.get<const BasicBlock *>()];
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for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) {
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const BasicBlock *BB = UME.Handler.get<const BasicBlock *>();
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UME.Handler = MBBMap[BB];
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}
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for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) {
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const BasicBlock *BB = CME.Handler.get<const BasicBlock *>();
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CME.Handler = MBBMap[BB];
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}
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}
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/// clear - Clear out all the function-specific state. This returns this
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/// FunctionLoweringInfo to an empty state, ready to be used for a
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/// different function.
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void FunctionLoweringInfo::clear() {
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MBBMap.clear();
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ValueMap.clear();
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StaticAllocaMap.clear();
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LiveOutRegInfo.clear();
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VisitedBBs.clear();
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ArgDbgValues.clear();
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ByValArgFrameIndexMap.clear();
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RegFixups.clear();
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StatepointStackSlots.clear();
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StatepointSpillMaps.clear();
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PreferredExtendType.clear();
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}
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/// CreateReg - Allocate a single virtual register for the given type.
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unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
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return RegInfo->createVirtualRegister(
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MF->getSubtarget().getTargetLowering()->getRegClassFor(VT));
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}
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/// CreateRegs - Allocate the appropriate number of virtual registers of
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/// the correctly promoted or expanded types. Assign these registers
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/// consecutive vreg numbers and return the first assigned number.
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///
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/// In the case that the given value has struct or array type, this function
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/// will assign registers for each member or element.
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///
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unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
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const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
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SmallVector<EVT, 4> ValueVTs;
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ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
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unsigned FirstReg = 0;
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for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
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EVT ValueVT = ValueVTs[Value];
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MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
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unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
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for (unsigned i = 0; i != NumRegs; ++i) {
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unsigned R = CreateReg(RegisterVT);
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if (!FirstReg) FirstReg = R;
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}
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}
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return FirstReg;
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}
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/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
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/// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
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/// the register's LiveOutInfo is for a smaller bit width, it is extended to
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/// the larger bit width by zero extension. The bit width must be no smaller
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/// than the LiveOutInfo's existing bit width.
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const FunctionLoweringInfo::LiveOutInfo *
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FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
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if (!LiveOutRegInfo.inBounds(Reg))
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return nullptr;
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LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
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if (!LOI->IsValid)
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return nullptr;
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if (BitWidth > LOI->KnownZero.getBitWidth()) {
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LOI->NumSignBits = 1;
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LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
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LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
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}
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return LOI;
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}
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/// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
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/// register based on the LiveOutInfo of its operands.
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void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
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Type *Ty = PN->getType();
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if (!Ty->isIntegerTy() || Ty->isVectorTy())
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return;
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SmallVector<EVT, 1> ValueVTs;
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ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
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assert(ValueVTs.size() == 1 &&
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"PHIs with non-vector integer types should have a single VT.");
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EVT IntVT = ValueVTs[0];
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if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
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return;
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IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
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unsigned BitWidth = IntVT.getSizeInBits();
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unsigned DestReg = ValueMap[PN];
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if (!TargetRegisterInfo::isVirtualRegister(DestReg))
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return;
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LiveOutRegInfo.grow(DestReg);
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LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
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Value *V = PN->getIncomingValue(0);
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if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
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DestLOI.NumSignBits = 1;
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APInt Zero(BitWidth, 0);
|
|
DestLOI.KnownZero = Zero;
|
|
DestLOI.KnownOne = Zero;
|
|
return;
|
|
}
|
|
|
|
if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
|
|
APInt Val = CI->getValue().zextOrTrunc(BitWidth);
|
|
DestLOI.NumSignBits = Val.getNumSignBits();
|
|
DestLOI.KnownZero = ~Val;
|
|
DestLOI.KnownOne = Val;
|
|
} else {
|
|
assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
|
|
"CopyToReg node was created.");
|
|
unsigned SrcReg = ValueMap[V];
|
|
if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
|
|
DestLOI.IsValid = false;
|
|
return;
|
|
}
|
|
const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
|
|
if (!SrcLOI) {
|
|
DestLOI.IsValid = false;
|
|
return;
|
|
}
|
|
DestLOI = *SrcLOI;
|
|
}
|
|
|
|
assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
|
|
DestLOI.KnownOne.getBitWidth() == BitWidth &&
|
|
"Masks should have the same bit width as the type.");
|
|
|
|
for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
|
|
Value *V = PN->getIncomingValue(i);
|
|
if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
|
|
DestLOI.NumSignBits = 1;
|
|
APInt Zero(BitWidth, 0);
|
|
DestLOI.KnownZero = Zero;
|
|
DestLOI.KnownOne = Zero;
|
|
return;
|
|
}
|
|
|
|
if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
|
|
APInt Val = CI->getValue().zextOrTrunc(BitWidth);
|
|
DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
|
|
DestLOI.KnownZero &= ~Val;
|
|
DestLOI.KnownOne &= Val;
|
|
continue;
|
|
}
|
|
|
|
assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
|
|
"its CopyToReg node was created.");
|
|
unsigned SrcReg = ValueMap[V];
|
|
if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
|
|
DestLOI.IsValid = false;
|
|
return;
|
|
}
|
|
const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
|
|
if (!SrcLOI) {
|
|
DestLOI.IsValid = false;
|
|
return;
|
|
}
|
|
DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
|
|
DestLOI.KnownZero &= SrcLOI->KnownZero;
|
|
DestLOI.KnownOne &= SrcLOI->KnownOne;
|
|
}
|
|
}
|
|
|
|
/// setArgumentFrameIndex - Record frame index for the byval
|
|
/// argument. This overrides previous frame index entry for this argument,
|
|
/// if any.
|
|
void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
|
|
int FI) {
|
|
ByValArgFrameIndexMap[A] = FI;
|
|
}
|
|
|
|
/// getArgumentFrameIndex - Get frame index for the byval argument.
|
|
/// If the argument does not have any assigned frame index then 0 is
|
|
/// returned.
|
|
int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
|
|
DenseMap<const Argument *, int>::iterator I =
|
|
ByValArgFrameIndexMap.find(A);
|
|
if (I != ByValArgFrameIndexMap.end())
|
|
return I->second;
|
|
DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
|
|
return 0;
|
|
}
|
|
|
|
unsigned FunctionLoweringInfo::getCatchPadExceptionPointerVReg(
|
|
const Value *CPI, const TargetRegisterClass *RC) {
|
|
MachineRegisterInfo &MRI = MF->getRegInfo();
|
|
auto I = CatchPadExceptionPointers.insert({CPI, 0});
|
|
unsigned &VReg = I.first->second;
|
|
if (I.second)
|
|
VReg = MRI.createVirtualRegister(RC);
|
|
assert(VReg && "null vreg in exception pointer table!");
|
|
return VReg;
|
|
}
|
|
|
|
/// ComputeUsesVAFloatArgument - Determine if any floating-point values are
|
|
/// being passed to this variadic function, and set the MachineModuleInfo's
|
|
/// usesVAFloatArgument flag if so. This flag is used to emit an undefined
|
|
/// reference to _fltused on Windows, which will link in MSVCRT's
|
|
/// floating-point support.
|
|
void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
|
|
MachineModuleInfo *MMI)
|
|
{
|
|
FunctionType *FT = cast<FunctionType>(
|
|
I.getCalledValue()->getType()->getContainedType(0));
|
|
if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
|
|
for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
|
|
Type* T = I.getArgOperand(i)->getType();
|
|
for (auto i : post_order(T)) {
|
|
if (i->isFloatingPointTy()) {
|
|
MMI->setUsesVAFloatArgument(true);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// AddLandingPadInfo - Extract the exception handling information from the
|
|
/// landingpad instruction and add them to the specified machine module info.
|
|
void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
|
|
MachineBasicBlock *MBB) {
|
|
if (const auto *PF = dyn_cast<Function>(
|
|
I.getParent()->getParent()->getPersonalityFn()->stripPointerCasts()))
|
|
MMI.addPersonality(PF);
|
|
|
|
if (I.isCleanup())
|
|
MMI.addCleanup(MBB);
|
|
|
|
// FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
|
|
// but we need to do it this way because of how the DWARF EH emitter
|
|
// processes the clauses.
|
|
for (unsigned i = I.getNumClauses(); i != 0; --i) {
|
|
Value *Val = I.getClause(i - 1);
|
|
if (I.isCatch(i - 1)) {
|
|
MMI.addCatchTypeInfo(MBB,
|
|
dyn_cast<GlobalValue>(Val->stripPointerCasts()));
|
|
} else {
|
|
// Add filters in a list.
|
|
Constant *CVal = cast<Constant>(Val);
|
|
SmallVector<const GlobalValue*, 4> FilterList;
|
|
for (User::op_iterator
|
|
II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
|
|
FilterList.push_back(cast<GlobalValue>((*II)->stripPointerCasts()));
|
|
|
|
MMI.addFilterTypeInfo(MBB, FilterList);
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned FunctionLoweringInfo::findSwiftErrorVReg(const MachineBasicBlock *MBB,
|
|
const Value* Val) const {
|
|
// Find the index in SwiftErrorVals.
|
|
SwiftErrorValues::const_iterator I =
|
|
std::find(SwiftErrorVals.begin(), SwiftErrorVals.end(), Val);
|
|
assert(I != SwiftErrorVals.end() && "Can't find value in SwiftErrorVals");
|
|
return SwiftErrorMap.lookup(MBB)[I - SwiftErrorVals.begin()];
|
|
}
|
|
|
|
void FunctionLoweringInfo::setSwiftErrorVReg(const MachineBasicBlock *MBB,
|
|
const Value* Val, unsigned VReg) {
|
|
// Find the index in SwiftErrorVals.
|
|
SwiftErrorValues::iterator I =
|
|
std::find(SwiftErrorVals.begin(), SwiftErrorVals.end(), Val);
|
|
assert(I != SwiftErrorVals.end() && "Can't find value in SwiftErrorVals");
|
|
SwiftErrorMap[MBB][I - SwiftErrorVals.begin()] = VReg;
|
|
}
|