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193 lines
4.8 KiB
193 lines
4.8 KiB
; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV
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; int f(int n, int d) {
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; if (n / d)
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; return 1;
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; return 0;
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; }
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define arm_aapcs_vfpcc i32 @f(i32 %n, i32 %d) {
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entry:
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%retval = alloca i32, align 4
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%n.addr = alloca i32, align 4
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%d.addr = alloca i32, align 4
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store i32 %n, i32* %n.addr, align 4
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store i32 %d, i32* %d.addr, align 4
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%0 = load i32, i32* %n.addr, align 4
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%1 = load i32, i32* %d.addr, align 4
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%div = sdiv i32 %0, %1
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%tobool = icmp ne i32 %div, 0
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br i1 %tobool, label %if.then, label %if.end
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if.then:
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store i32 1, i32* %retval, align 4
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br label %return
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if.end:
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store i32 0, i32* %retval, align 4
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br label %return
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return:
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%2 = load i32, i32* %retval, align 4
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ret i32 %2
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}
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; CHECK-DIV-DAG: BB#0
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; CHECK-DIV-DAG: Successors according to CFG: BB#5({{.*}}) BB#4
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; CHECK-DIV-DAG: BB#1
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; CHECK-DIV-DAG: Successors according to CFG: BB#3
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; CHECK-DIV-DAG: BB#2
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; CHECK-DIV-DAG: Successors according to CFG: BB#3
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; CHECK-DIV-DAG: BB#3
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; CHECK-DIV-DAG: BB#4
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; CHECK-DIV-DAG: Successors according to CFG: BB#1({{.*}}) BB#2
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; CHECK-DIV-DAG: BB#5
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; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD
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; int r;
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; int g(int l, int m) {
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; if (m <= 0)
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; return 0;
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; return (r = l % m);
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; }
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@r = common global i32 0, align 4
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define arm_aapcs_vfpcc i32 @g(i32 %l, i32 %m) {
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entry:
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%cmp = icmp eq i32 %m, 0
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br i1 %cmp, label %return, label %if.end
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if.end:
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%rem = urem i32 %l, %m
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store i32 %rem, i32* @r, align 4
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br label %return
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return:
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%retval.0 = phi i32 [ %rem, %if.end ], [ 0, %entry ]
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ret i32 %retval.0
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}
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; CHECK-MOD-DAG: BB#0
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; CHECK-MOD-DAG: Successors according to CFG: BB#2({{.*}}) BB#1
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; CHECK-MOD-DAG: BB#1
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; CHECK-MOD-DAG: Successors according to CFG: BB#4({{.*}}) BB#3
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; CHECK-MOD-DAG: BB#2
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; CHECK-MOD-DAG: BB#3
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; CHECK-MOD-DAG: Successors according to CFG: BB#2
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; CHECK-MOD-DAG: BB#4
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; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG
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; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM
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; unsigned c;
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; extern unsigned long g(void);
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; int f(unsigned u, signed char b) {
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; if (b)
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; c = g() % u;
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; return c;
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; }
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@c = common global i32 0, align 4
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declare arm_aapcs_vfpcc i32 @i()
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define arm_aapcs_vfpcc i32 @h(i32 %u, i8 signext %b) #0 {
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entry:
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%tobool = icmp eq i8 %b, 0
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br i1 %tobool, label %entry.if.end_crit_edge, label %if.then
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entry.if.end_crit_edge:
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%.pre = load i32, i32* @c, align 4
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br label %if.end
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if.then:
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%call = tail call arm_aapcs_vfpcc i32 @i()
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%rem = urem i32 %call, %u
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store i32 %rem, i32* @c, align 4
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br label %if.end
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if.end:
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%0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %rem, %if.then ]
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ret i32 %0
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}
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attributes #0 = { optsize }
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; CHECK-CFG-DAG: BB#0
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; CHECK-CFG-DAG: t2Bcc <BB#2>
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; CHECK-CFG-DAG: t2B <BB#1>
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; CHECK-CFG-DAG: BB#1
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; CHECK-CFG-DAG: t2B <BB#3>
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; CHECK-CFG-DAG: BB#2
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; CHECK-CFG-DAG: tCBZ %vreg{{[0-9]}}, <BB#5>
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; CHECK-CFG-DAG: t2B <BB#4>
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; CHECK-CFG-DAG: BB#4
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; CHECK-CFG-DAG: BB#3
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; CHECK-CFG-DAG: tBX_RET
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; CHECK-CFG-DAG: BB#5
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; CHECK-CFG-DAG: t2UDF 249
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; CHECK-CFG-ASM-LABEL: h:
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; CHECK-CFG-ASM: cbz r{{[0-9]}}, .LBB2_2
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; CHECK-CFG-ASM: b .LBB2_4
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; CHECK-CFG-ASM-LABEL: .LBB2_2:
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; CHECK-CFG-ASM-NEXT: udf.w #249
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; CHECK-CFG-ASM-LABEL: .LBB2_4:
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; CHECK-CFG-ASM: bl __rt_udiv
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; CHECK-CFG-ASM: pop.w {{{.*}}, r11, pc}
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; RUN: llc -O0 -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-WIN__DBZCHK
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; long k(void);
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; int l(void);
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; int j(int i) {
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; if (l() == -1)
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; return 0;
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; return k() % i;
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; }
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declare arm_aapcs_vfpcc i32 @k()
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declare arm_aapcs_vfpcc i32 @l()
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define arm_aapcs_vfpcc i32 @j(i32 %i) {
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entry:
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%retval = alloca i32, align 4
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%i.addr = alloca i32, align 4
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store i32 %i, i32* %i.addr, align 4
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%call = call arm_aapcs_vfpcc i32 @l()
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%cmp = icmp eq i32 %call, -1
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 0, i32* %retval, align 4
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br label %return
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if.end:
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%call1 = call arm_aapcs_vfpcc i32 @k()
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%0 = load i32, i32* %i.addr, align 4
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%rem = srem i32 %call1, %0
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store i32 %rem, i32* %retval, align 4
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br label %return
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return:
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%1 = load i32, i32* %retval, align 4
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ret i32 %1
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}
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; CHECK-WIN__DBZCHK-LABEL: j:
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; CHECK-WIN__DBZCHK: cbz r{{[0-7]}}, .LBB
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; CHECK-WIN__DBZCHK-NOT: cbz r8, .LBB
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; CHECK-WIN__DBZCHK-NOT: cbz r9, .LBB
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; CHECK-WIN__DBZCHK-NOT: cbz r10, .LBB
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; CHECK-WIN__DBZCHK-NOT: cbz r11, .LBB
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; CHECK-WIN__DBZCHK-NOT: cbz ip, .LBB
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; CHECK-WIN__DBZCHK-NOT: cbz lr, .LBB
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