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198 lines
4.9 KiB
198 lines
4.9 KiB
; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
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; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s
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; Hexagon Programmer's Reference Manual 11.1.1 ALU32/ALU
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; CHECK-CALL-NOT: call
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; Add
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declare i32 @llvm.hexagon.A2.addi(i32, i32)
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define i32 @A2_addi(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.addi(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: = add({{.*}}, #0)
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declare i32 @llvm.hexagon.A2.add(i32, i32)
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define i32 @A2_add(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.add(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = add({{.*}}, {{.*}})
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declare i32 @llvm.hexagon.A2.addsat(i32, i32)
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define i32 @A2_addsat(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.addsat(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = add({{.*}}, {{.*}}):sat
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; Logical operations
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declare i32 @llvm.hexagon.A2.and(i32, i32)
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define i32 @A2_and(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.and(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = and({{.*}}, {{.*}})
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declare i32 @llvm.hexagon.A2.or(i32, i32)
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define i32 @A2_or(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.or(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = or({{.*}}, {{.*}})
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declare i32 @llvm.hexagon.A2.xor(i32, i32)
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define i32 @A2_xor(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.xor(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = xor({{.*}}, {{.*}})
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declare i32 @llvm.hexagon.A4.andn(i32, i32)
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define i32 @A4_andn(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A4.andn(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = and({{.*}}, ~{{.*}})
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declare i32 @llvm.hexagon.A4.orn(i32, i32)
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define i32 @A4_orn(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A4.orn(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = or({{.*}}, ~{{.*}})
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; Subtract
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declare i32 @llvm.hexagon.A2.sub(i32, i32)
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define i32 @A2_sub(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.sub(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = sub({{.*}}, {{.*}})
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declare i32 @llvm.hexagon.A2.subsat(i32, i32)
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define i32 @A2_subsat(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.subsat(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = sub({{.*}}, {{.*}}):sat
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; Sign extend
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declare i32 @llvm.hexagon.A2.sxtb(i32)
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define i32 @A2_sxtb(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.sxtb(i32 %a)
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ret i32 %z
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}
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; CHECK: = sxtb({{.*}})
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declare i32 @llvm.hexagon.A2.sxth(i32)
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define i32 @A2_sxth(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.sxth(i32 %a)
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ret i32 %z
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}
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; CHECK: = sxth({{.*}})
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; Transfer immediate
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declare i32 @llvm.hexagon.A2.tfril(i32, i32)
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define i32 @A2_tfril(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.tfril(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: = #0
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declare i32 @llvm.hexagon.A2.tfrih(i32, i32)
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define i32 @A2_tfrih(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.tfrih(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: = #0
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declare i32 @llvm.hexagon.A2.tfrsi(i32)
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define i32 @A2_tfrsi() {
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%z = call i32 @llvm.hexagon.A2.tfrsi(i32 0)
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ret i32 %z
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}
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; CHECK: = #0
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; Transfer register
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declare i32 @llvm.hexagon.A2.tfr(i32)
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define i32 @A2_tfr(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.tfr(i32 %a)
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ret i32 %z
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}
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; CHECK: =
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; Vector add halfwords
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declare i32 @llvm.hexagon.A2.svaddh(i32, i32)
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define i32 @A2_svaddh(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.svaddh(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = vaddh({{.*}}, {{.*}})
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declare i32 @llvm.hexagon.A2.svaddhs(i32, i32)
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define i32 @A2_svaddhs(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.svaddhs(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = vaddh({{.*}}, {{.*}}):sat
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declare i32 @llvm.hexagon.A2.svadduhs(i32, i32)
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define i32 @A2_svadduhs(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.svadduhs(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = vadduh({{.*}}, {{.*}}):sat
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; Vector average halfwords
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declare i32 @llvm.hexagon.A2.svavgh(i32, i32)
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define i32 @A2_svavgh(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.svavgh(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = vavgh({{.*}}, {{.*}})
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declare i32 @llvm.hexagon.A2.svavghs(i32, i32)
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define i32 @A2_svavghs(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.svavghs(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = vavgh({{.*}}, {{.*}}):rnd
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declare i32 @llvm.hexagon.A2.svnavgh(i32, i32)
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define i32 @A2_svnavgh(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.svnavgh(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = vnavgh({{.*}}, {{.*}})
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; Vector subtract halfwords
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declare i32 @llvm.hexagon.A2.svsubh(i32, i32)
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define i32 @A2_svsubh(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.svsubh(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = vsubh({{.*}}, {{.*}})
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declare i32 @llvm.hexagon.A2.svsubhs(i32, i32)
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define i32 @A2_svsubhs(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.svsubhs(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = vsubh({{.*}}, {{.*}}):sat
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declare i32 @llvm.hexagon.A2.svsubuhs(i32, i32)
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define i32 @A2_svsubuhs(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.svsubuhs(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: = vsubuh({{.*}}, {{.*}}):sat
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; Zero extend
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declare i32 @llvm.hexagon.A2.zxth(i32)
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define i32 @A2_zxth(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.zxth(i32 %a)
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ret i32 %z
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}
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; CHECK: = zxth({{.*}})
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