king
/
v811_spc009
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'a2ed455462'
${ noResults }
v811_spc009/external/llvm/test/CodeGen/MIR/Lanai/peephole-compare.mir

715 lines
18 KiB
Raw Blame History

# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s
# Test the compare fold peephole.
# CHECK-LABEL: name: test0a
# TODO: Enhance combiner to handle this case. This expands into:
# sub %r7, %r6, %r3
# sub.f %r7, %r6, %r0
# sel.eq %r18, %r3, %rv
# This is different from the pattern currently matched. If the lowered form had
# been sub.f %r3, 0, %r0 then it would have matched.
# CHECK-LABEL: name: test1a
# CHECK: [[IN1:%.*]] = COPY %r7
# CHECK: [[IN2:%.*]] = COPY %r6
# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
# CHECK-LABEL: name: test1b
# CHECK: [[IN1:%.*]] = COPY %r7
# CHECK: [[IN2:%.*]] = COPY %r6
# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
# CHECK-LABEL: name: test2a
# CHECK: [[IN1:%.*]] = COPY %r7
# CHECK: [[IN2:%.*]] = COPY %r6
# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
# CHECK-LABEL: name: test2b
# CHECK: [[IN1:%.*]] = COPY %r7
# CHECK: [[IN2:%.*]] = COPY %r6
# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr
# CHECK-LABEL: name: test3
# CHECK: AND_F_R
# CHECK: AND_F_R
# CHECK: AND_F_R
--- |
target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
target triple = "lanai-unknown-unknown"
@a = global i32 -1, align 4
@b = global i32 0, align 4
define i32 @test0a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
entry:
%sub = sub i32 %b, %a
%cmp = icmp eq i32 %sub, 0
%cond = select i1 %cmp, i32 %c, i32 %sub
ret i32 %cond
}
define i32 @test0b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
entry:
%cmp = icmp eq i32 %b, %a
%cond = select i1 %cmp, i32 %c, i32 %b
ret i32 %cond
}
define i32 @test1a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
entry:
%sub = sub i32 %b, %a
%cmp = icmp slt i32 %sub, 0
%cond = select i1 %cmp, i32 %c, i32 %d
ret i32 %cond
}
define i32 @test1b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
entry:
%sub = sub i32 %b, %a
%cmp = icmp slt i32 %sub, 0
%cond = select i1 %cmp, i32 %c, i32 %d
ret i32 %cond
}
define i32 @test2a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
entry:
%sub = sub i32 %b, %a
%cmp = icmp sgt i32 %sub, -1
%cond = select i1 %cmp, i32 %c, i32 %d
ret i32 %cond
}
define i32 @test2b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
entry:
%sub = sub i32 %b, %a
%cmp = icmp sgt i32 %sub, -1
%cond = select i1 %cmp, i32 %c, i32 %d
ret i32 %cond
}
define i32 @test3(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
entry:
%sub = sub i32 %b, %a
%cmp = icmp slt i32 %sub, 1
%cond = select i1 %cmp, i32 %c, i32 %d
ret i32 %cond
}
define i32 @test4(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
entry:
%cmp = icmp ne i32 %a, 0
%cmp1 = icmp ult i32 %a, %b
%or.cond = and i1 %cmp, %cmp1
br i1 %or.cond, label %return, label %if.end
if.end: ; preds = %entry
%cmp2 = icmp ne i32 %b, 0
%cmp4 = icmp ult i32 %b, %c
%or.cond29 = and i1 %cmp2, %cmp4
br i1 %or.cond29, label %return, label %if.end6
if.end6: ; preds = %if.end
%cmp7 = icmp ne i32 %c, 0
%cmp9 = icmp ult i32 %c, %d
%or.cond30 = and i1 %cmp7, %cmp9
br i1 %or.cond30, label %return, label %if.end11
if.end11: ; preds = %if.end6
%cmp12 = icmp ne i32 %d, 0
%cmp14 = icmp ult i32 %d, %a
%or.cond31 = and i1 %cmp12, %cmp14
%b. = select i1 %or.cond31, i32 %b, i32 21
ret i32 %b.
return: ; preds = %if.end6, %if.end, %entry
%retval.0 = phi i32 [ %c, %entry ], [ %d, %if.end ], [ %a, %if.end6 ]
ret i32 %retval.0
}
define void @testBB() {
entry:
%0 = load i32, i32* @a, align 4, !tbaa !0
%1 = load i32, i32* @b, align 4, !tbaa !0
%sub.i = sub i32 %1, %0
%tobool = icmp sgt i32 %sub.i, -1
br i1 %tobool, label %if.end, label %if.then
if.then: ; preds = %entry
%call1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
br label %while.body
while.body: ; preds = %while.body, %if.then
br label %while.body
if.end: ; preds = %entry
%cmp.i = icmp slt i32 %sub.i, 1
br i1 %cmp.i, label %if.then4, label %if.end7
if.then4: ; preds = %if.end
%call5 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
br label %while.body6
while.body6: ; preds = %while.body6, %if.then4
br label %while.body6
if.end7: ; preds = %if.end
ret void
}
declare i32 @g(...)
; Function Attrs: nounwind
declare void @llvm.stackprotector(i8*, i8**) #0
attributes #0 = { nounwind }
!0 = !{!1, !1, i64 0}
!1 = !{!"int", !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C/C++ TBAA"}
...
---
name: test0a
alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
- { id: 5, class: gpr }
liveins:
- { reg: '%r6', virtual-reg: '%0' }
- { reg: '%r7', virtual-reg: '%1' }
- { reg: '%r18', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
liveins: %r6, %r7, %r18
%2 = COPY %r18
%1 = COPY %r7
%0 = COPY %r6
%4 = SUB_R %1, %0, 0
SFSUB_F_RI_LO %4, 0, implicit-def %sr
%5 = SELECT %2, %4, 7, implicit %sr
%rv = COPY %5
RET implicit %rca, implicit %rv
...
---
name: test0b
alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
liveins:
- { reg: '%r6', virtual-reg: '%0' }
- { reg: '%r7', virtual-reg: '%1' }
- { reg: '%r18', virtual-reg: '%2' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
liveins: %r6, %r7, %r18
%2 = COPY %r18
%1 = COPY %r7
%0 = COPY %r6
SFSUB_F_RR %1, %0, implicit-def %sr
%4 = SELECT %2, %1, 7, implicit %sr
%rv = COPY %4
RET implicit %rca, implicit %rv
...
---
name: test1a
alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
- { id: 5, class: gpr }
liveins:
- { reg: '%r6', virtual-reg: '%0' }
- { reg: '%r7', virtual-reg: '%1' }
- { reg: '%r18', virtual-reg: '%2' }
- { reg: '%r19', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
liveins: %r6, %r7, %r18, %r19
%3 = COPY %r19
%2 = COPY %r18
%1 = COPY %r7
%0 = COPY %r6
%4 = SUB_R %1, %0, 0
SFSUB_F_RI_LO killed %4, 0, implicit-def %sr
%5 = SELECT %2, %3, 11, implicit %sr
%rv = COPY %5
RET implicit %rca, implicit %rv
...
---
name: test1b
alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
- { id: 5, class: gpr }
liveins:
- { reg: '%r6', virtual-reg: '%0' }
- { reg: '%r7', virtual-reg: '%1' }
- { reg: '%r18', virtual-reg: '%2' }
- { reg: '%r19', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
liveins: %r6, %r7, %r18, %r19
%3 = COPY %r19
%2 = COPY %r18
%1 = COPY %r7
%0 = COPY %r6
%4 = SUB_R %1, %0, 0
SFSUB_F_RI_LO killed %4, 0, implicit-def %sr
%5 = SELECT %2, %3, 11, implicit %sr
%rv = COPY %5
RET implicit %rca, implicit %rv
...
---
name: test2a
alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
- { id: 5, class: gpr }
liveins:
- { reg: '%r6', virtual-reg: '%0' }
- { reg: '%r7', virtual-reg: '%1' }
- { reg: '%r18', virtual-reg: '%2' }
- { reg: '%r19', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
liveins: %r6, %r7, %r18, %r19
%3 = COPY %r19
%2 = COPY %r18
%1 = COPY %r7
%0 = COPY %r6
%4 = SUB_R %1, %0, 0
SFSUB_F_RI_LO killed %4, 0, implicit-def %sr
%5 = SELECT %2, %3, 10, implicit %sr
%rv = COPY %5
RET implicit %rca, implicit %rv
...
---
name: test2b
alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
- { id: 5, class: gpr }
liveins:
- { reg: '%r6', virtual-reg: '%0' }
- { reg: '%r7', virtual-reg: '%1' }
- { reg: '%r18', virtual-reg: '%2' }
- { reg: '%r19', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
liveins: %r6, %r7, %r18, %r19
%3 = COPY %r19
%2 = COPY %r18
%1 = COPY %r7
%0 = COPY %r6
%4 = SUB_R %1, %0, 0
SFSUB_F_RI_LO killed %4, 0, implicit-def %sr
%5 = SELECT %2, %3, 10, implicit %sr
%rv = COPY %5
RET implicit %rca, implicit %rv
...
---
name: test3
alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
- { id: 5, class: gpr }
liveins:
- { reg: '%r6', virtual-reg: '%0' }
- { reg: '%r7', virtual-reg: '%1' }
- { reg: '%r18', virtual-reg: '%2' }
- { reg: '%r19', virtual-reg: '%3' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
liveins: %r6, %r7, %r18, %r19
%3 = COPY %r19
%2 = COPY %r18
%1 = COPY %r7
%0 = COPY %r6
%4 = SUB_R %1, %0, 0
SFSUB_F_RI_LO killed %4, 1, implicit-def %sr
%5 = SELECT %2, %3, 13, implicit %sr
%rv = COPY %5
RET implicit %rca, implicit %rv
...
---
name: test4
alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
- { id: 5, class: gpr }
- { id: 6, class: gpr }
- { id: 7, class: gpr }
- { id: 8, class: gpr }
- { id: 9, class: gpr }
- { id: 10, class: gpr }
- { id: 11, class: gpr }
- { id: 12, class: gpr }
- { id: 13, class: gpr }
- { id: 14, class: gpr }
- { id: 15, class: gpr }
- { id: 16, class: gpr }
- { id: 17, class: gpr }
- { id: 18, class: gpr }
- { id: 19, class: gpr }
- { id: 20, class: gpr }
- { id: 21, class: gpr }
- { id: 22, class: gpr }
liveins:
- { reg: '%r6', virtual-reg: '%1' }
- { reg: '%r7', virtual-reg: '%2' }
- { reg: '%r18', virtual-reg: '%3' }
- { reg: '%r19', virtual-reg: '%4' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
successors: %bb.4.return, %bb.1.if.end
liveins: %r6, %r7, %r18, %r19
%4 = COPY %r19
%3 = COPY %r18
%2 = COPY %r7
%1 = COPY %r6
SFSUB_F_RI_LO %1, 0, implicit-def %sr
%5 = SCC 6, implicit %sr
SFSUB_F_RR %1, %2, implicit-def %sr
%6 = SCC 4, implicit %sr
%7 = AND_R killed %5, killed %6, 0
%8 = SLI 1
%9 = AND_R killed %7, %8, 0
SFSUB_F_RI_LO killed %9, 0, implicit-def %sr
BRCC %bb.4.return, 6, implicit %sr
BT %bb.1.if.end
bb.1.if.end:
successors: %bb.4.return, %bb.2.if.end6
SFSUB_F_RI_LO %2, 0, implicit-def %sr
%10 = SCC 6, implicit %sr
SFSUB_F_RR %2, %3, implicit-def %sr
%11 = SCC 4, implicit %sr
%12 = AND_R killed %10, killed %11, 0
%14 = AND_R killed %12, %8, 0
SFSUB_F_RI_LO killed %14, 0, implicit-def %sr
BRCC %bb.4.return, 6, implicit %sr
BT %bb.2.if.end6
bb.2.if.end6:
successors: %bb.4.return, %bb.3.if.end11
SFSUB_F_RI_LO %3, 0, implicit-def %sr
%15 = SCC 6, implicit %sr
SFSUB_F_RR %3, %4, implicit-def %sr
%16 = SCC 4, implicit %sr
%17 = AND_R killed %15, killed %16, 0
%18 = SLI 1
%19 = AND_R killed %17, killed %18, 0
SFSUB_F_RI_LO killed %19, 0, implicit-def %sr
BRCC %bb.4.return, 6, implicit %sr
BT %bb.3.if.end11
bb.3.if.end11:
%20 = SLI 21
SFSUB_F_RR %4, %1, implicit-def %sr
%21 = SELECT %2, %20, 4, implicit %sr
SFSUB_F_RI_LO %4, 0, implicit-def %sr
%22 = SELECT killed %21, %20, 6, implicit %sr
%rv = COPY %22
RET implicit %rca, implicit %rv
bb.4.return:
%0 = PHI %3, %bb.0.entry, %4, %bb.1.if.end, %1, %bb.2.if.end6
%rv = COPY %0
RET implicit %rca, implicit %rv
...
---
name: testBB
alignment: 2
exposesReturnsTwice: false
hasInlineAsm: false
allVRegsAllocated: false
isSSA: true
tracksRegLiveness: true
tracksSubRegLiveness: false
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
- { id: 5, class: gpr }
- { id: 6, class: gpr }
- { id: 7, class: gpr }
- { id: 8, class: gpr }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: true
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0.entry:
successors: %bb.3.if.end, %bb.1.if.then
%1 = MOVHI target-flags(lanai-hi) @a
%2 = OR_I_LO killed %1, target-flags(lanai-lo) @a
%3 = LDW_RI killed %2, 0, 0 :: (load 4 from @a, !tbaa !0)
%4 = MOVHI target-flags(lanai-hi) @b
%5 = OR_I_LO killed %4, target-flags(lanai-lo) @b
%6 = LDW_RI killed %5, 0, 0 :: (load 4 from @b, !tbaa !0)
%0 = SUB_R killed %6, killed %3, 0
SFSUB_F_RI_LO %0, 0, implicit-def %sr
BRCC %bb.3.if.end, 10, implicit %sr
BT %bb.1.if.then
bb.1.if.then:
successors: %bb.2.while.body
ADJCALLSTACKDOWN 0, implicit-def dead %sp, implicit %sp
CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
bb.2.while.body:
successors: %bb.2.while.body
BT %bb.2.while.body
bb.3.if.end:
successors: %bb.4.if.then4, %bb.6.if.end7
liveins: %sr
BRCC %bb.6.if.end7, 14, implicit %sr
BT %bb.4.if.then4
bb.4.if.then4:
successors: %bb.5.while.body6
ADJCALLSTACKDOWN 0, implicit-def dead %sp, implicit %sp
CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
bb.5.while.body6:
successors: %bb.5.while.body6
BT %bb.5.while.body6
bb.6.if.end7:
RET implicit %rca
...
Reference in new issue View Git Blame Copy Permalink