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86 lines
3.1 KiB
86 lines
3.1 KiB
/*
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* Copyright 2014 Google Inc.
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*
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifndef SkHalf_DEFINED
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#define SkHalf_DEFINED
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#include "SkNx.h"
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#include "SkTypes.h"
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// 16-bit floating point value
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// format is 1 bit sign, 5 bits exponent, 10 bits mantissa
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// only used for storage
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typedef uint16_t SkHalf;
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static constexpr uint16_t SK_HalfMin = 0x0400; // 2^-14 (minimum positive normal value)
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static constexpr uint16_t SK_HalfMax = 0x7bff; // 65504
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static constexpr uint16_t SK_HalfEpsilon = 0x1400; // 2^-10
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static constexpr uint16_t SK_Half1 = 0x3C00; // 1
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// convert between half and single precision floating point
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float SkHalfToFloat(SkHalf h);
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SkHalf SkFloatToHalf(float f);
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// Convert between half and single precision floating point,
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// assuming inputs and outputs are both finite, and may
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// flush values which would be denormal half floats to zero.
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static inline Sk4f SkHalfToFloat_finite_ftz(uint64_t);
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static inline Sk4h SkFloatToHalf_finite_ftz(const Sk4f&);
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// ~~~~~~~~~~~ impl ~~~~~~~~~~~~~~ //
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// Like the serial versions in SkHalf.cpp, these are based on
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// https://fgiesen.wordpress.com/2012/03/28/half-to-float-done-quic/
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// GCC 4.9 lacks the intrinsics to use ARMv8 f16<->f32 instructions, so we use inline assembly.
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static inline Sk4f SkHalfToFloat_finite_ftz(uint64_t rgba) {
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Sk4h hs = Sk4h::Load(&rgba);
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#if !defined(SKNX_NO_SIMD) && defined(SK_CPU_ARM64)
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float32x4_t fs;
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asm ("fcvtl %[fs].4s, %[hs].4h \n" // vcvt_f32_f16(...)
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: [fs] "=w" (fs) // =w: write-only NEON register
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: [hs] "w" (hs.fVec)); // w: read-only NEON register
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return fs;
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#else
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Sk4i bits = SkNx_cast<int>(hs), // Expand to 32 bit.
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sign = bits & 0x00008000, // Save the sign bit for later...
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positive = bits ^ sign, // ...but strip it off for now.
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is_norm = 0x03ff < positive; // Exponent > 0?
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// For normal half floats, extend the mantissa by 13 zero bits,
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// then adjust the exponent from 15 bias to 127 bias.
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Sk4i norm = (positive << 13) + ((127 - 15) << 23);
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Sk4i merged = (sign << 16) | (norm & is_norm);
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return Sk4f::Load(&merged);
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#endif
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}
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static inline Sk4h SkFloatToHalf_finite_ftz(const Sk4f& fs) {
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#if !defined(SKNX_NO_SIMD) && defined(SK_CPU_ARM64)
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float32x4_t vec = fs.fVec;
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asm ("fcvtn %[vec].4h, %[vec].4s \n" // vcvt_f16_f32(vec)
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: [vec] "+w" (vec)); // +w: read-write NEON register
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return vreinterpret_u16_f32(vget_low_f32(vec));
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#else
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Sk4i bits = Sk4i::Load(&fs),
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sign = bits & 0x80000000, // Save the sign bit for later...
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positive = bits ^ sign, // ...but strip it off for now.
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will_be_norm = 0x387fdfff < positive; // greater than largest denorm half?
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// For normal half floats, adjust the exponent from 127 bias to 15 bias,
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// then drop the bottom 13 mantissa bits.
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Sk4i norm = (positive - ((127 - 15) << 23)) >> 13;
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Sk4i merged = (sign >> 16) | (will_be_norm & norm);
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return SkNx_cast<uint16_t>(merged);
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#endif
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}
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#endif
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