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367 lines
12 KiB
367 lines
12 KiB
// Copyright 2016, VIXL authors
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// Test description for instructions of the following forms:
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// MNEMONIC{<c>}.W <Rd>, <Rn>, <Rm>
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// MNEMONIC{<c>}.W <Rd>, SP, <Rm>
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// MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> }
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// MNEMONIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> }
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//
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// MNEMONIC{<c>}.N <Rdm>, SP, <Rdm>
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// MNEMONIC{<c>}.N SP, SP, <Rm>
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// MNEMONIC{<c>}.N <Rd>, <Rn>, <Rm>
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// MNEMONIC{<c>}.N <Rdn>, <Rdn>, <Rm> ; rm is not SP
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// MNEMONIC{<c>}.N <Rdn>, <Rdn>, <Rm> ; low registers
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//
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// Note that this test only covers the cases where the optional shift
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// operand is not provided. The shift operands are tested in
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// "cond-rd-rn-operand-rm-shift-amount-*-t32.json".
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{
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"mnemonics": [
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"Adc", // ADC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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// ADC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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"Adcs", // ADCS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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// ADCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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"Add", // ADD<c>{<q>} <Rd>, <Rn>, <Rm> ; T1
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// ADD<c>{<q>} <Rdn>, <Rm> ; T2
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// ADD{<c>}{<q>} {<Rdn>}, <Rdn>, <Rm> ; T2
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// ADD{<c>}{<q>} {<Rdm>}, SP, <Rdm> ; T1
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// ADD{<c>}{<q>} {SP}, SP, <Rm> ; T2
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// ADD{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
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// ADD{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
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"Adds", // ADDS{<q>} {<Rd>}, <Rn>, <Rm> ; T1
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// ADDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T3
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// ADDS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T3
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"And", // AND<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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// AND{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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"Ands", // ANDS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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// ANDS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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"Bic", // BIC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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// BIC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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"Bics", // BICS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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// BICS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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"Eor", // EOR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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// EOR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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"Eors", // EORS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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// EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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"Orn", // ORN{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
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"Orns", // ORNS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
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"Orr", // ORR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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// ORR{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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"Orrs", // ORRS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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// ORRS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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"Rsb", // RSB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
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"Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T1
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"Sbc", // SBC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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// SBC{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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"Sbcs", // SBCS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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// SBCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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"Sub", // SUB<c>{<q>} <Rd>, <Rn>, <Rm> ; T1
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// SUB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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// SUB{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1
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// SUB{<c>} {<Rd>}, SP, <Rm> ; T1
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"Subs", // SUBS{<q>} {<Rd>}, <Rn>, <Rm> ; T1
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// SUBS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
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// SUBS{<c>}{<q>} {<Rd>}, SP, <Rm> {, <shift> #<amount> } ; T1
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"Sxtab", // SXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
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"Sxtab16", // SXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
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"Sxtah", // SXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
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"Uxtab", // UXTAB{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
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"Uxtab16", // UXTAB16{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
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"Uxtah", // UXTAH{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, ROR #<amount> } ; T1
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// Shift instructions that alias to MOV.
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// Note that we are not giving them a different input for their
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// last operand since they are already tested in
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// "cond-rd-operand-rn-shift-rs-t32.json".
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// TODO: Add tests for MOV <Rd>, <Rn>, <shift>, <Rs>.
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"Asr", // ASR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
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// ASR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
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"Asrs", // ASRS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
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// ASRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
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"Lsl", // LSL<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
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// LSL{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
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"Lsls", // LSLS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
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// LSLS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
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"Lsr", // LSR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
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// LSR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
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"Lsrs", // LSRS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
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// LSRS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
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"Ror", // ROR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
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// ROR{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
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"Rors" // RORS{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
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// RORS{<c>}{<q>} {<Rd>}, <Rm>, <Rs> ; T2
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],
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"description": {
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"operands": [
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{
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"name": "cond",
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"type": "Condition"
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},
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{
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"name": "rd",
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"type": "AllRegistersButPC"
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},
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{
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"name": "rn",
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"type": "AllRegistersButPC"
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},
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{
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"name": "op",
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"wrapper": "Operand",
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"operands": [
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{
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"name": "rm",
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"type": "AllRegistersButPC"
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}
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]
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}
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],
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"inputs": [
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{
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"name": "apsr",
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"type": "NZCV"
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},
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{
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"name": "rd",
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"type": "Register"
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},
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{
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"name": "rn",
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"type": "Register"
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},
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{
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"name": "rm",
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"type": "Register"
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}
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]
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},
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"test-files": [
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{
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"type": "assembler",
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"test-cases": [
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{
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"name": "Unconditionnal",
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"operands": [
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"cond", "rd", "rn", "rm"
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],
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"operand-filter": "cond == 'al'",
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"operand-limit": 500
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}
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]
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},
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// Test cases where an IT instruction is allowed.
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{
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"name": "all-low-in-it-block",
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"type": "assembler",
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"mnemonics": [
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"Add", // ADD<c>{<q>} <Rd>, <Rn>, <Rm> ; T1
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"Sub" // SUB<c>{<q>} <Rd>, <Rn>, <Rm> ; T1
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],
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"test-cases": [
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{
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"name": "InITBlock",
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"operands": [
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"cond", "rd", "rn", "rm"
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],
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// Generate an extra IT instruction.
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"in-it-block": "{cond}",
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"operand-filter": "cond != 'al' and register_is_low(rd) and register_is_low(rn) and register_is_low(rm)",
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"operand-limit": 500
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}
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]
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},
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{
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"name": "all-low-rd-is-rn-in-it-block",
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"type": "assembler",
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"mnemonics": [
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"Adc", // ADC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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"And", // AND<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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"Asr", // ASR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
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"Bic", // BIC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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"Eor", // EOR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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"Lsl", // LSL<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
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"Lsr", // LSR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
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"Orr", // ORR<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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"Ror", // ROR<c>{<q>} {<Rdm>}, <Rdm>, <Rs> ; T1
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"Sbc" // SBC<c>{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
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],
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"test-cases": [
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{
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"name": "InITBlock",
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"operands": [
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"cond", "rd", "rn", "rm"
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],
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// Generate an extra IT instruction.
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"in-it-block": "{cond}",
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"operand-filter": "cond != 'al' and rd == rn and register_is_low(rn) and register_is_low(rm)",
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"operand-limit": 500
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}
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]
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},
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{
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"name": "rd-is-rn-in-it-block",
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"type": "assembler",
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"mnemonics": [
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"Add" // ADD{<c>}{<q>} {<Rdn>}, <Rdn>, <Rm> ; T2
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],
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"test-cases": [
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{
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"name": "InITBlock",
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"operands": [
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"cond", "rd", "rn", "rm"
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],
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// Generate an extra IT instruction.
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"in-it-block": "{cond}",
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"operand-filter": "cond != 'al' and rd == rn and rm != 'r13'",
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"operand-limit": 500
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}
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]
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},
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// Special case for a conditional ADD instruction with rn as SP.
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{
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"name": "rn-is-sp-in-it-block",
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"type": "assembler",
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"mnemonics": [
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"Add" // ADD{<c>}{<q>} {<Rdm>}, SP, <Rdm> ; T1
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],
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"test-cases": [
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{
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"name": "InITBlock",
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"operands": [
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"cond", "rd", "rn", "rm"
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],
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// Generate an extra IT instruction.
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"in-it-block": "{cond}",
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"operand-filter": "cond != 'al' and rd == rm and register_is_low(rm) and rn == 'r13'"
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}
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]
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},
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// Special case for a conditional ADD instruction with rd and rn as SP.
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{
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"name": "rd-is-rn-is-sp-in-it-block",
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"type": "assembler",
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"mnemonics": [
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"Add" // ADD{<c>}{<q>} {SP}, SP, <Rm> ; T2
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],
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"test-cases": [
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{
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"name": "InITBlock",
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"operands": [
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"cond", "rd", "rn", "rm"
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],
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// Generate an extra IT instruction.
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"in-it-block": "{cond}",
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"operand-filter": "cond != 'al' and rd == 'r13' and rn == 'r13'"
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}
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]
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},
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{
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"type": "simulator",
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"test-cases": [
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{
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"name": "Condition",
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"operands": [
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"cond"
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],
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"inputs": [
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"apsr"
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]
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},
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// Test combinations of registers values with rd == rn.
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{
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"name": "RdIsRn",
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"operands": [
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"cond", "rd", "rn", "rm"
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],
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"inputs": [
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"apsr", "rd", "rn", "rm"
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],
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"operand-filter": "rd == rn and rn != rm",
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"operand-limit": 10,
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"input-filter": "rd == rn",
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"input-limit": 200
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},
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// Test combinations of registers values with rd == rm.
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{
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"name": "RdIsRm",
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"operands": [
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"cond", "rd", "rn", "rm"
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],
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"inputs": [
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"apsr", "rd", "rn", "rm"
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],
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"operand-filter": "rd == rm and rn != rm",
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"operand-limit": 10,
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"input-filter": "rd == rm",
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"input-limit": 200
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},
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// Test combinations of registers values.
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{
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"name": "RdIsNotRnIsNotRm",
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"operands": [
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"cond", "rd", "rn", "rm"
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],
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"inputs": [
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"apsr", "rd", "rn", "rm"
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],
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"operand-filter": "rd != rn != rm",
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"operand-limit": 10,
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"input-limit": 200
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}
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]
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}
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]
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}
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