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739 lines
19 KiB
739 lines
19 KiB
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MSMB_ISP__
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#define __MSMB_ISP__
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#include <linux/videodev2.h>
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#define MAX_PLANES_PER_STREAM 3
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#define MAX_NUM_STREAM 7
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#define ISP_VERSION_47 47
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#define ISP_VERSION_46 46
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#define ISP_VERSION_44 44
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#define ISP_VERSION_40 40
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#define ISP_VERSION_32 32
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#define ISP_NATIVE_BUF_BIT (0x10000 << 0)
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#define ISP0_BIT (0x10000 << 1)
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#define ISP1_BIT (0x10000 << 2)
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#define ISP_META_CHANNEL_BIT (0x10000 << 3)
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#define ISP_SCRATCH_BUF_BIT (0x10000 << 4)
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#define ISP_STATS_STREAM_BIT 0x80000000
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struct msm_vfe_cfg_cmd_list;
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enum ISP_START_PIXEL_PATTERN {
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ISP_BAYER_RGRGRG,
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ISP_BAYER_GRGRGR,
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ISP_BAYER_BGBGBG,
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ISP_BAYER_GBGBGB,
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ISP_YUV_YCbYCr,
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ISP_YUV_YCrYCb,
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ISP_YUV_CbYCrY,
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ISP_YUV_CrYCbY,
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ISP_PIX_PATTERN_MAX
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};
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enum msm_vfe_plane_fmt {
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Y_PLANE,
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CB_PLANE,
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CR_PLANE,
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CRCB_PLANE,
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CBCR_PLANE,
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VFE_PLANE_FMT_MAX
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};
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enum msm_vfe_input_src {
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VFE_PIX_0,
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VFE_RAW_0,
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VFE_RAW_1,
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VFE_RAW_2,
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VFE_SRC_MAX,
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};
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enum msm_vfe_axi_stream_src {
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PIX_ENCODER,
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PIX_VIEWFINDER,
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PIX_VIDEO,
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CAMIF_RAW,
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IDEAL_RAW,
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RDI_INTF_0,
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RDI_INTF_1,
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RDI_INTF_2,
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VFE_AXI_SRC_MAX
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};
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enum msm_vfe_frame_skip_pattern {
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NO_SKIP,
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EVERY_2FRAME,
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EVERY_3FRAME,
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EVERY_4FRAME,
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EVERY_5FRAME,
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EVERY_6FRAME,
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EVERY_7FRAME,
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EVERY_8FRAME,
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EVERY_16FRAME,
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EVERY_32FRAME,
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SKIP_ALL,
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SKIP_RANGE,
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MAX_SKIP,
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};
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enum msm_isp_stats_type {
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MSM_ISP_STATS_AEC, /* legacy based AEC */
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MSM_ISP_STATS_AF, /* legacy based AF */
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MSM_ISP_STATS_AWB, /* legacy based AWB */
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MSM_ISP_STATS_RS, /* legacy based RS */
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MSM_ISP_STATS_CS, /* legacy based CS */
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MSM_ISP_STATS_IHIST, /* legacy based HIST */
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MSM_ISP_STATS_SKIN, /* legacy based SKIN */
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MSM_ISP_STATS_BG, /* Bayer Grids */
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MSM_ISP_STATS_BF, /* Bayer Focus */
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MSM_ISP_STATS_BE, /* Bayer Exposure*/
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MSM_ISP_STATS_BHIST, /* Bayer Hist */
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MSM_ISP_STATS_BF_SCALE, /* Bayer Focus scale */
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MSM_ISP_STATS_HDR_BE, /* HDR Bayer Exposure */
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MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */
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MSM_ISP_STATS_AEC_BG, /* AEC BG */
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MSM_ISP_STATS_MAX /* MAX */
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};
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/*
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* @stats_type_mask: Stats type mask (enum msm_isp_stats_type).
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* @stream_src_mask: Stream src mask (enum msm_vfe_axi_stream_src)
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* @skip_mode: skip pattern, if skip mode is range only then min/max is used
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* @min_frame_id: minimum frame id (valid only if skip_mode = RANGE)
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* @max_frame_id: maximum frame id (valid only if skip_mode = RANGE)
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*/
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struct msm_isp_sw_framskip {
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uint32_t stats_type_mask;
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uint32_t stream_src_mask;
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enum msm_vfe_frame_skip_pattern skip_mode;
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uint32_t min_frame_id;
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uint32_t max_frame_id;
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};
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enum msm_vfe_testgen_color_pattern {
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COLOR_BAR_8_COLOR,
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UNICOLOR_WHITE,
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UNICOLOR_YELLOW,
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UNICOLOR_CYAN,
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UNICOLOR_GREEN,
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UNICOLOR_MAGENTA,
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UNICOLOR_RED,
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UNICOLOR_BLUE,
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UNICOLOR_BLACK,
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MAX_COLOR,
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};
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enum msm_vfe_camif_input {
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CAMIF_DISABLED,
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CAMIF_PAD_REG_INPUT,
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CAMIF_MIDDI_INPUT,
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CAMIF_MIPI_INPUT,
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};
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struct msm_vfe_fetch_engine_cfg {
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uint32_t input_format;
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uint32_t buf_width;
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uint32_t buf_height;
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uint32_t fetch_width;
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uint32_t fetch_height;
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uint32_t x_offset;
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uint32_t y_offset;
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uint32_t buf_stride;
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};
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/*
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* Camif output general configuration
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*/
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struct msm_vfe_camif_subsample_cfg {
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uint32_t irq_subsample_period;
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uint32_t irq_subsample_pattern;
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uint32_t sof_counter_step;
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uint32_t pixel_skip;
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uint32_t line_skip;
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};
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/*
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* Camif frame and window configuration
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*/
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struct msm_vfe_camif_cfg {
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uint32_t lines_per_frame;
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uint32_t pixels_per_line;
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uint32_t first_pixel;
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uint32_t last_pixel;
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uint32_t first_line;
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uint32_t last_line;
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uint32_t epoch_line0;
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uint32_t epoch_line1;
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uint32_t hbi_cnt;
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enum msm_vfe_camif_input camif_input;
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struct msm_vfe_camif_subsample_cfg subsample_cfg;
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};
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struct msm_vfe_testgen_cfg {
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uint32_t lines_per_frame;
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uint32_t pixels_per_line;
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uint32_t v_blank;
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uint32_t h_blank;
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enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern;
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uint32_t rotate_period;
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enum msm_vfe_testgen_color_pattern color_bar_pattern;
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uint32_t burst_num_frame;
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};
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enum msm_vfe_inputmux {
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CAMIF,
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TESTGEN,
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EXTERNAL_READ,
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};
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enum msm_vfe_stats_composite_group {
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STATS_COMPOSITE_GRP_NONE,
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STATS_COMPOSITE_GRP_1,
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STATS_COMPOSITE_GRP_2,
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STATS_COMPOSITE_GRP_MAX,
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};
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struct msm_vfe_pix_cfg {
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struct msm_vfe_camif_cfg camif_cfg;
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struct msm_vfe_testgen_cfg testgen_cfg;
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struct msm_vfe_fetch_engine_cfg fetch_engine_cfg;
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enum msm_vfe_inputmux input_mux;
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enum ISP_START_PIXEL_PATTERN pixel_pattern;
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uint32_t input_format;
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uint32_t is_split;
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};
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struct msm_vfe_rdi_cfg {
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uint8_t cid;
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uint8_t frame_based;
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};
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struct msm_vfe_input_cfg {
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union {
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struct msm_vfe_pix_cfg pix_cfg;
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struct msm_vfe_rdi_cfg rdi_cfg;
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} d;
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enum msm_vfe_input_src input_src;
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uint32_t input_pix_clk;
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};
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struct msm_vfe_fetch_eng_start {
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uint32_t session_id;
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uint32_t stream_id;
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uint32_t buf_idx;
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uint32_t buf_addr;
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};
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struct msm_vfe_axi_plane_cfg {
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uint32_t output_width; /*Include padding*/
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uint32_t output_height;
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uint32_t output_stride;
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uint32_t output_scan_lines;
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uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/
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uint32_t plane_addr_offset;
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uint8_t csid_src; /*RDI 0-2*/
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uint8_t rdi_cid;/*CID 1-16*/
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};
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enum msm_stream_memory_input_t {
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MEMORY_INPUT_DISABLED,
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MEMORY_INPUT_ENABLED
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};
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struct msm_vfe_axi_stream_request_cmd {
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uint32_t session_id;
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uint32_t stream_id;
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uint32_t vt_enable;
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uint32_t output_format;/*Planar/RAW/Misc*/
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enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/
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struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
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uint32_t burst_count;
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uint32_t hfr_mode;
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uint8_t frame_base;
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uint32_t init_frame_drop; /*MAX 31 Frames*/
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enum msm_vfe_frame_skip_pattern frame_skip_pattern;
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uint8_t buf_divert; /* if TRUE no vb2 buf done. */
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/*Return values*/
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uint32_t axi_stream_handle;
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uint32_t controllable_output;
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uint32_t burst_len;
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/* Flag indicating memory input stream */
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enum msm_stream_memory_input_t memory_input;
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};
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struct msm_vfe_axi_stream_release_cmd {
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uint32_t stream_handle;
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};
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enum msm_vfe_axi_stream_cmd {
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STOP_STREAM,
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START_STREAM,
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STOP_IMMEDIATELY,
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};
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struct msm_vfe_axi_stream_cfg_cmd {
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uint8_t num_streams;
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uint32_t stream_handle[MAX_NUM_STREAM];
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enum msm_vfe_axi_stream_cmd cmd;
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};
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enum msm_vfe_axi_stream_update_type {
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ENABLE_STREAM_BUF_DIVERT,
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DISABLE_STREAM_BUF_DIVERT,
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UPDATE_STREAM_FRAMEDROP_PATTERN,
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UPDATE_STREAM_STATS_FRAMEDROP_PATTERN,
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UPDATE_STREAM_AXI_CONFIG,
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UPDATE_STREAM_REQUEST_FRAMES,
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UPDATE_STREAM_ADD_BUFQ,
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UPDATE_STREAM_REMOVE_BUFQ,
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UPDATE_STREAM_SW_FRAME_DROP,
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};
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enum msm_vfe_iommu_type {
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IOMMU_ATTACH,
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IOMMU_DETACH,
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};
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enum msm_vfe_buff_queue_id {
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VFE_BUF_QUEUE_DEFAULT,
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VFE_BUF_QUEUE_SHARED,
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VFE_BUF_QUEUE_MAX,
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};
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struct msm_vfe_axi_stream_cfg_update_info {
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uint32_t stream_handle;
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uint32_t output_format;
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uint32_t user_stream_id;
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uint32_t frame_id;
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enum msm_vfe_frame_skip_pattern skip_pattern;
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struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
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struct msm_isp_sw_framskip sw_skip_info;
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};
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struct msm_vfe_axi_halt_cmd {
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uint32_t stop_camif;
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uint32_t overflow_detected;
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uint32_t blocking_halt;
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};
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struct msm_vfe_axi_reset_cmd {
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uint32_t blocking;
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uint32_t frame_id;
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};
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struct msm_vfe_axi_restart_cmd {
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uint32_t enable_camif;
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};
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struct msm_vfe_axi_stream_update_cmd {
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uint32_t num_streams;
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enum msm_vfe_axi_stream_update_type update_type;
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struct msm_vfe_axi_stream_cfg_update_info
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update_info[MSM_ISP_STATS_MAX];
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};
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struct msm_vfe_smmu_attach_cmd {
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uint32_t security_mode;
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uint32_t iommu_attach_mode;
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};
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struct msm_vfe_stats_stream_request_cmd {
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uint32_t session_id;
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uint32_t stream_id;
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enum msm_isp_stats_type stats_type;
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uint32_t composite_flag;
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uint32_t framedrop_pattern;
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uint32_t init_frame_drop; /*MAX 31 Frames*/
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uint32_t irq_subsample_pattern;
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uint32_t buffer_offset;
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uint32_t stream_handle;
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};
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struct msm_vfe_stats_stream_release_cmd {
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uint32_t stream_handle;
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};
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struct msm_vfe_stats_stream_cfg_cmd {
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uint8_t num_streams;
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uint32_t stream_handle[MSM_ISP_STATS_MAX];
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uint8_t enable;
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uint32_t stats_burst_len;
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};
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enum msm_vfe_reg_cfg_type {
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VFE_WRITE,
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VFE_WRITE_MB,
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VFE_READ,
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VFE_CFG_MASK,
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VFE_WRITE_DMI_16BIT,
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VFE_WRITE_DMI_32BIT,
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VFE_WRITE_DMI_64BIT,
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VFE_READ_DMI_16BIT,
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VFE_READ_DMI_32BIT,
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VFE_READ_DMI_64BIT,
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GET_MAX_CLK_RATE,
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GET_CLK_RATES,
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GET_ISP_ID,
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VFE_HW_UPDATE_LOCK,
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VFE_HW_UPDATE_UNLOCK,
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SET_WM_UB_SIZE,
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SET_UB_POLICY,
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};
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struct msm_vfe_cfg_cmd2 {
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uint16_t num_cfg;
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uint16_t cmd_len;
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void __user *cfg_data;
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void __user *cfg_cmd;
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};
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struct msm_vfe_cfg_cmd_list {
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struct msm_vfe_cfg_cmd2 cfg_cmd;
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struct msm_vfe_cfg_cmd_list *next;
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uint32_t next_size;
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};
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struct msm_vfe_reg_rw_info {
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uint32_t reg_offset;
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uint32_t cmd_data_offset;
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uint32_t len;
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};
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struct msm_vfe_reg_mask_info {
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uint32_t reg_offset;
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uint32_t mask;
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uint32_t val;
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};
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struct msm_vfe_reg_dmi_info {
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uint32_t hi_tbl_offset; /*Optional*/
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uint32_t lo_tbl_offset; /*Required*/
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uint32_t len;
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};
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struct msm_vfe_reg_cfg_cmd {
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union {
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struct msm_vfe_reg_rw_info rw_info;
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struct msm_vfe_reg_mask_info mask_info;
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struct msm_vfe_reg_dmi_info dmi_info;
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} u;
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enum msm_vfe_reg_cfg_type cmd_type;
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};
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enum msm_isp_buf_type {
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ISP_PRIVATE_BUF,
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ISP_SHARE_BUF,
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MAX_ISP_BUF_TYPE,
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};
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struct msm_isp_buf_request {
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uint32_t session_id;
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uint32_t stream_id;
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uint8_t num_buf;
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uint32_t handle;
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enum msm_isp_buf_type buf_type;
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};
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struct msm_isp_qbuf_plane {
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uint32_t addr;
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uint32_t offset;
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uint32_t length;
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};
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struct msm_isp_qbuf_buffer {
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struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM];
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uint32_t num_planes;
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};
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struct msm_isp_qbuf_info {
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uint32_t handle;
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int32_t buf_idx;
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/*Only used for prepare buffer*/
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struct msm_isp_qbuf_buffer buffer;
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/*Only used for diverted buffer*/
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uint32_t dirty_buf;
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};
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struct msm_isp_clk_rates {
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uint32_t nominal_rate;
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uint32_t high_rate;
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};
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struct msm_vfe_axi_src_state {
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enum msm_vfe_input_src input_src;
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uint32_t src_active;
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uint32_t src_frame_id;
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};
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enum msm_isp_event_mask_index {
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ISP_EVENT_MASK_INDEX_STATS_NOTIFY = 0,
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ISP_EVENT_MASK_INDEX_ERROR = 1,
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ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT = 2,
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ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE = 3,
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ISP_EVENT_MASK_INDEX_REG_UPDATE = 4,
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ISP_EVENT_MASK_INDEX_SOF = 5,
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ISP_EVENT_MASK_INDEX_BUF_DIVERT = 6,
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ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY = 7,
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ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE = 8
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};
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#define ISP_EVENT_SUBS_MASK_NONE 0
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#define ISP_EVENT_SUBS_MASK_STATS_NOTIFY \
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(1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY)
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#define ISP_EVENT_SUBS_MASK_ERROR \
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(1 << ISP_EVENT_MASK_INDEX_ERROR)
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#define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT \
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(1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT)
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#define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE \
|
|
(1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE)
|
|
|
|
#define ISP_EVENT_SUBS_MASK_REG_UPDATE \
|
|
(1 << ISP_EVENT_MASK_INDEX_REG_UPDATE)
|
|
|
|
#define ISP_EVENT_SUBS_MASK_SOF \
|
|
(1 << ISP_EVENT_MASK_INDEX_SOF)
|
|
|
|
#define ISP_EVENT_SUBS_MASK_BUF_DIVERT \
|
|
(1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT)
|
|
|
|
#define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY \
|
|
(1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY)
|
|
|
|
#define ISP_EVENT_SUBS_MASK_FE_READ_DONE \
|
|
(1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE)
|
|
|
|
enum msm_isp_event_idx {
|
|
ISP_REG_UPDATE = 0,
|
|
ISP_EPOCH_0 = 1,
|
|
ISP_EPOCH_1 = 2,
|
|
ISP_START_ACK = 3,
|
|
ISP_STOP_ACK = 4,
|
|
ISP_IRQ_VIOLATION = 5,
|
|
ISP_STATS_OVERFLOW = 6,
|
|
ISP_BUF_DONE = 7,
|
|
ISP_FE_RD_DONE = 8,
|
|
ISP_IOMMU_P_FAULT = 9,
|
|
ISP_ERROR = 10,
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|
ISP_PING_PONG_MISMATCH = 11,
|
|
ISP_REG_UPDATE_MISSING = 12,
|
|
ISP_EVENT_MAX = 13
|
|
};
|
|
|
|
#define ISP_EVENT_OFFSET 8
|
|
#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START)
|
|
#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET))
|
|
#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET))
|
|
#define ISP_CAMIF_EVENT_BASE (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET))
|
|
#define ISP_STREAM_EVENT_BASE (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET))
|
|
#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE)
|
|
#define ISP_EVENT_EPOCH_0 (ISP_EVENT_BASE + ISP_EPOCH_0)
|
|
#define ISP_EVENT_EPOCH_1 (ISP_EVENT_BASE + ISP_EPOCH_1)
|
|
#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK)
|
|
#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK)
|
|
#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION)
|
|
#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW)
|
|
#define ISP_EVENT_ERROR (ISP_EVENT_BASE + ISP_ERROR)
|
|
#define ISP_EVENT_SOF (ISP_CAMIF_EVENT_BASE)
|
|
#define ISP_EVENT_EOF (ISP_CAMIF_EVENT_BASE + 1)
|
|
#define ISP_EVENT_BUF_DONE (ISP_EVENT_BASE + ISP_BUF_DONE)
|
|
#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE)
|
|
#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE)
|
|
#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX)
|
|
#define ISP_EVENT_FE_READ_DONE (ISP_EVENT_BASE + ISP_FE_RD_DONE)
|
|
#define ISP_EVENT_IOMMU_P_FAULT (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT)
|
|
#define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH)
|
|
#define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING)
|
|
#define ISP_EVENT_STREAM_UPDATE_DONE (ISP_STREAM_EVENT_BASE)
|
|
|
|
/* The msm_v4l2_event_data structure should match the
|
|
* v4l2_event.u.data field.
|
|
* should not exceed 64 bytes */
|
|
|
|
struct msm_isp_buf_event {
|
|
uint32_t session_id;
|
|
uint32_t stream_id;
|
|
uint32_t handle;
|
|
uint32_t output_format;
|
|
int8_t buf_idx;
|
|
};
|
|
struct msm_isp_stats_event {
|
|
uint32_t stats_mask; /* 4 bytes */
|
|
uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */
|
|
};
|
|
|
|
struct msm_isp_stream_ack {
|
|
uint32_t session_id;
|
|
uint32_t stream_id;
|
|
uint32_t handle;
|
|
};
|
|
|
|
enum msm_vfe_error_type {
|
|
ISP_ERROR_NONE,
|
|
ISP_ERROR_CAMIF,
|
|
ISP_ERROR_BUS_OVERFLOW,
|
|
ISP_ERROR_RETURN_EMPTY_BUFFER,
|
|
ISP_ERROR_FRAME_ID_MISMATCH,
|
|
ISP_ERROR_MAX,
|
|
};
|
|
|
|
struct msm_isp_error_info {
|
|
enum msm_vfe_error_type err_type;
|
|
uint32_t session_id;
|
|
uint32_t stream_id;
|
|
};
|
|
|
|
struct msm_isp_output_info {
|
|
uint32_t regs_not_updated;
|
|
uint32_t output_err_mask;
|
|
uint16_t stream_framedrop_mask;
|
|
uint32_t stats_framedrop_mask;
|
|
uint32_t axi_updating_mask;
|
|
};
|
|
|
|
struct msm_isp_event_data {
|
|
/*Wall clock except for buffer divert events
|
|
*which use monotonic clock
|
|
*/
|
|
struct timeval timestamp;
|
|
/* Monotonic timestamp since bootup */
|
|
struct timeval mono_timestamp;
|
|
uint32_t frame_id;
|
|
union {
|
|
struct msm_isp_stats_event stats;
|
|
struct msm_isp_buf_event buf_done;
|
|
struct msm_isp_error_info error_info;
|
|
struct msm_isp_output_info output_info;
|
|
} u; /* union can have max 52 bytes */
|
|
};
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
struct msm_isp_event_data32 {
|
|
struct compat_timeval timestamp;
|
|
struct compat_timeval mono_timestamp;
|
|
uint32_t frame_id;
|
|
union {
|
|
struct msm_isp_stats_event stats;
|
|
struct msm_isp_buf_event buf_done;
|
|
struct msm_isp_error_info error_info;
|
|
struct msm_isp_output_info output_info;
|
|
} u;
|
|
};
|
|
#endif
|
|
|
|
#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8')
|
|
#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8')
|
|
#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8')
|
|
#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8')
|
|
#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0')
|
|
#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0')
|
|
#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0')
|
|
#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0')
|
|
#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2')
|
|
#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2')
|
|
#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2')
|
|
#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2')
|
|
#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4')
|
|
#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4')
|
|
#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4')
|
|
#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4')
|
|
#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0')
|
|
#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0')
|
|
#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0')
|
|
#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0')
|
|
#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4')
|
|
#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1')
|
|
#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T')
|
|
#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.GRGR.*/
|
|
#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.RGRG.*/
|
|
#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') /* 14 GRGR.BGBG.*/
|
|
#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.GBGB.*/
|
|
|
|
#define VIDIOC_MSM_VFE_REG_CFG \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2)
|
|
|
|
#define VIDIOC_MSM_ISP_REQUEST_BUF \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request)
|
|
|
|
#define VIDIOC_MSM_ISP_ENQUEUE_BUF \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info)
|
|
|
|
#define VIDIOC_MSM_ISP_RELEASE_BUF \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request)
|
|
|
|
#define VIDIOC_MSM_ISP_REQUEST_STREAM \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd)
|
|
|
|
#define VIDIOC_MSM_ISP_CFG_STREAM \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd)
|
|
|
|
#define VIDIOC_MSM_ISP_RELEASE_STREAM \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd)
|
|
|
|
#define VIDIOC_MSM_ISP_INPUT_CFG \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg)
|
|
|
|
#define VIDIOC_MSM_ISP_SET_SRC_STATE \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state)
|
|
|
|
#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+9, \
|
|
struct msm_vfe_stats_stream_request_cmd)
|
|
|
|
#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd)
|
|
|
|
#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+11, \
|
|
struct msm_vfe_stats_stream_release_cmd)
|
|
|
|
#define VIDIOC_MSM_ISP_REG_UPDATE_CMD \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+12, enum msm_vfe_input_src)
|
|
|
|
#define VIDIOC_MSM_ISP_UPDATE_STREAM \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd)
|
|
|
|
#define VIDIOC_MSM_VFE_REG_LIST_CFG \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+14, struct msm_vfe_cfg_cmd_list)
|
|
|
|
#define VIDIOC_MSM_ISP_SMMU_ATTACH \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+15, struct msm_vfe_smmu_attach_cmd)
|
|
|
|
#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+16, struct msm_vfe_axi_stream_update_cmd)
|
|
|
|
#define VIDIOC_MSM_ISP_AXI_HALT \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+17, struct msm_vfe_axi_halt_cmd)
|
|
|
|
#define VIDIOC_MSM_ISP_AXI_RESET \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+18, struct msm_vfe_axi_reset_cmd)
|
|
|
|
#define VIDIOC_MSM_ISP_AXI_RESTART \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+19, struct msm_vfe_axi_restart_cmd)
|
|
|
|
#define VIDIOC_MSM_ISP_FETCH_ENG_START \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+20, struct msm_vfe_fetch_eng_start)
|
|
|
|
#define VIDIOC_MSM_ISP_DEQUEUE_BUF \
|
|
_IOWR('V', BASE_VIDIOC_PRIVATE+21, struct msm_isp_qbuf_info)
|
|
|
|
#endif /* __MSMB_ISP__ */
|