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79 lines
2.6 KiB
79 lines
2.6 KiB
/*
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* Copyright (c) Hisilicon Technologies Co., Ltd. 2014-2020. All rights reserved.
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* Description: cpu ids code
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* Author: SmartMedia_BSP
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* Create: 2014-06-04
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*/
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#ifndef CPUIDSH
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#define CPUIDSH
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#define RESERVED13 (932610816LL)
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#define RESERVED13_C (932610832LL)
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#define RESERVED13_D (3272147200LL)
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#define RESERVED13_MASK (0xFFFFFFFFFFLL)
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#define RESERVED9 (932610817LL)
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#define RESERVED9_C (932610833LL)
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#define RESERVED9_D (3272147201LL)
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#define RESERVED9_MASK (0xFFFFFFFFFFLL)
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#ifdef CONFIG_SOCT_SLS_B
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#define RESERVED19_B_SYSID (0xC3020200L)
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#define RESERVED19_B (RESERVED19_B_SYSID | (0x1LL << 32))
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#elif defined(CONFIG_SOCT_SLS_C)
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#define RESERVED19_C_SYSID (0x19060812L)
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#define RESERVED19_C (RESERVED19_C_SYSID | (0x1LL << 32))
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#define HI3751V811_C_SYSID (0x19060812L)
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#define HI3751V811_C (HI3751V811_C_SYSID | (0x1LL << 32))
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#else
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#define RESERVED19_SYSID (0x19060810L)
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#define RESERVED19 (RESERVED19_SYSID | (0x1LL << 32))
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#endif
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#define RESERVED5_B_SYSID (0xc3030100L)
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#define RESERVED5_B (RESERVED5_B_SYSID | (0x1LL << 32))
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#define T9_SYSID_MASK (0xFFFFFFFFL)
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#define T9_MASK (T9_SYSID_MASK | (0xFLL << 32))
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/* The support device every chip platform */
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#define DEV_HLNFC_AUTO 0x01
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#define DEV_HLNFC301 0x02
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#define DEV_HLNFC504 0x03
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#define DEV_HLNFC610 0x04
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#define DEV_HLFMC100 0x05
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#define DEV_HLNFC_MASK 0x0F
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#define DEV_EMMC_AUTO 0x10
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#define DEV_EMMCV100 0x20
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#define DEV_EMMCV200 0x20
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#define DEV_EMMC_MASK 0xF0
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#define DEV_HLSFC_AUTO 0x100
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#define DEV_HLSFC300 0x200
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#define DEV_HLSFC350 0x300
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#define DEV_NOR_HLFMC100 0x500
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#define DEV_HLSFC_MASK 0xF00
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/* bootstrap type */
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#define SELF_BOOT_TYPE_NONE (0) /* boot type: NONE SELF BOOT */
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#define SELF_BOOT_TYPE_UART (1) /* boot type: UART */
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#define SELF_BOOT_TYPE_USBDEV (2) /* boot type: USBDEV */
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#define SELF_BOOT_TYPE_USBHOST (3) /* boot type: USBHOST */
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/* chipset ca type */
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#define CHIPSET_CATYPE_INVALID (-1) /* chipset catype: invalid type */
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#define CHIPSET_CATYPE_NORMAL (0) /* chipset catype: NORMAL */
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#define CHIPSET_CATYPE_CA (1) /* chipset catype: CA */
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/* board type */
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#define BOARD_TYPE_0 0x1
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#define BOARD_TYPE_1 0x2
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#define BOARD_TYPE_2 0x3
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#define BOARD_TYPE_RESERVED 0x10
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#define BOARD_TYPE_INVALID 0x11
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#endif /* CPUIDSH */
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