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/*
* Copyright (c) Hisilicon Technologies Co., Ltd. 2012-2019. All rights reserved.
* Description: decoder
* Author: Hisilicon
* Create: 2012-04-22
*/
#ifndef _DMCU_DBG_H_
#define _DMCU_DBG_H_
#include "td_type.h"
#include "soc_osal.h"
#define PROC_LINE_LENGTH 102 /* 102 is the Length of a line of characters */
#define PROC_SHELL_LENGTH 192
#define PROC_LOG_LENGTH 154
#define PROC_IOMMU_LENGTH 126
#define DMCU_TEST_VAM 1
#define MEM_TEST_ARGC_MAX_LEN 4
#define MEM_TEST_DEFAULT_LOOP 1
/* dmcu_cmd_proc_himm */
#define MD_MAX_LEN 128
#define REG_VALUE_LEN 4
typedef enum {
DMCU_CMD_HELP,
DMCU_CMD_MALLOC,
DMCU_CMD_FREE,
DMCU_CMD_MAP,
DMCU_CMD_POOL,
DMCU_CMD_BULK,
DMCU_CMD_TEST_MAX
} dmcu_test_cmd;
typedef union {
struct {
td_u32 pmp_init : 1; /* 0 */
td_u32 rpmsg_init : 1; /* 1 */
td_u32 drv_mbx_init : 1; /* 2 */
td_u32 dmcu_comm_ctrl_init : 1; /* 3 */
td_u32 drv_ipcm_init : 1; /* 4 */
td_u32 drv_ipcm_open : 1; /* 5 */
td_u32 dmcu_server_ctrl_init : 1; /* 6 */
td_u32 ctrl_thread_status : 5; /* 7 - 11 */
td_u32 soc_log_init : 1; /* 12 */
td_u32 dmcu_dbg_init : 1; /* 13 */
td_u32 dmcu_mem_init : 1; /* 14 */
td_u32 pq_dmcu_server_init : 1; /* 15 */
td_u32 drv_dmcu_server_init : 1; /* 16 */
td_u32 drv_panel_dmcu_server_init : 1; /* 17 */
td_u32 reserved : 14;
} bit;
td_u32 u32;
} mcu_dmcu_status;
mcu_dmcu_status *get_mcu_status(td_void);
td_u32 dmcu_iommu_test(td_s32 argc, const char **argv);
td_void dmcu_cmd_shell_proc_init(td_void);
td_void dmcu_cmd_log_proc_init(td_void);
td_s32 dmcu_dbg_init(td_void);
#endif /* _DMCU_DBG_H_ */