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137 lines
3.7 KiB
137 lines
3.7 KiB
/*
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* Copyright (c) Hisilicon Technologies Co., Ltd. 2012-2019. All rights reserved.
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* Description: decoder
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* Author: Hisilicon
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* Create: 2012-04-22
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*/
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#ifndef _DMCU_HAL_H_
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#define _DMCU_HAL_H_
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#include "td_type.h"
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#include "soc_osal.h"
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#include "drv_dmcu_sys.h"
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#define IOMMU_SEC_IRQ_NUM (26 + 4)
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#define IOMMU_NO_SEC_IRQ_NUM (26 + 5)
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#define MEM_PT_SIZE_MAX 0x400000
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#define MEM_MAX_ADDR 0xffffffff
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#if (defined(LOSCFG_FAMILY_RESERVED19) || defined(LOSCFG_FAMILY_HI3751V811))
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#define SMMU_SCR 0x0
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#define COMMON_CTRL 0x4
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#define INT_MASK_SEC 0x10
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#define INT_CLR_SEC 0x1C
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#define INT_MASK_NO_SEC 0x20
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#define INT_CLR_NO_SEC 0x2C
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#define SCB_TTBR 0x2E4
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#define SCB_TTBR_H 0x2E0
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#define CB_TTBR 0x2EC
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#define CB_TTBR_H 0x2E8
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#define ERR_S_RD_ADDR 0x2F0
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#define ERR_S_RD_ADDR_H 0x2F4
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#define ERR_S_WR_ADDR 0x2FC
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#define ERR_S_WR_ADDR_H 0x2F8
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#define ERR_NS_RD_ADDR 0x304
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#define ERR_NS_RD_ADDR_H 0x300
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#define ERR_NS_WR_ADDR 0x30C
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#define ERR_NS_WR_ADDR_H 0x308
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#define CMD_BUF_STATE 0x20
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#define TLB_FLUSH 0x58
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#define IOMMU_MAP_SIZE 0x1000
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#define DMCU_MAX_PT_SIZE (4 * 1024 * 1024)
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#else
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#define SMMU_SCR 0x0
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#define COMMON_CTRL 0x4
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#define CLK_GT_EN 0x8
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#define INT_MASK_SEC 0x10
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#define INT_CLR_SEC 0x1C
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#define INT_MASK_NO_SEC 0x20
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#define INT_CLR_NO_SEC 0x2C
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#define SCB_TTBR 0x100
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#define SCB_TTBR_H 0x104
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#define CB_TTBR 0x200
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#define CB_TTBR_H 0x204
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#define SCMD_TAG_RD_EN 0x110
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#define SCMD_TAG_WR_EN 0x120
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#define ERR_S_RD_ADDR 0x130
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#define ERR_S_RD_ADDR_H 0x134
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#define ERR_S_WR_ADDR 0x138
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#define ERR_S_WR_ADDR_H 0x13c
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#define CMD_TAG_RD_EN 0x210
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#define CMD_TAG_WR_EN 0x220
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#define ERR_NS_RD_ADDR 0x230
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#define ERR_NS_RD_ADDR_H 0x234
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#define ERR_NS_WR_ADDR 0x238
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#define ERR_NS_WR_ADDR_H 0x23c
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#define CMD_BUF_STATE 0x20
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#define COMMON_TCU 0x10
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#define TLB_FLUSH 0x58
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#define IOMMU_MAP_SIZE 0x1000
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#define DMCU_MAX_PT_SIZE (4 * 1024 * 1024)
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#endif
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#define DCMAINT 0x7C3
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#define write_custom_csr(reg_addr, val) \
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do { \
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if (__builtin_constant_p(val) && (unsigned int)(val) < 32) \
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__asm__ __volatile__("li t0, " \
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"%0" ::"i"(val)); \
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else \
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__asm__ __volatile__("mv t0, " \
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"%0" ::"r"(val)); \
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__asm__ __volatile__("csrw %0, t0" ::"i"(reg_addr)); \
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} while (0)
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typedef enum {
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DMCU_IOMMU_ERR_ADDR_RD_SEC = 0,
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DMCU_IOMMU_ERR_ADDR_WR_SEC = 1,
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DMCU_IOMMU_ERR_ADDR_RD_NON_SEC = 2,
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DMCU_IOMMU_ERR_ADDR_WR_NON_SEC = 3,
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DMCU_IOMMU_ERR_ADDR_MAX,
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} iommu_err_addr_index;
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#define DMCU_IOMMU_REG_INFO_SIZE 0x400
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#define DMCU_IOMMU_ERR_ADDR_SIZE 256
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#define wr_iommu_reg_(data, reg) \
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do { \
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*(volatile td_u32 *)(reg) = (data); \
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} while (0)
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#define rd_iommu_reg_(data, reg) \
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do { \
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(data) = *(volatile td_u32 *)(reg); \
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} while (0)
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#define WR_IOMMU_REG wr_iommu_reg_
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#define RD_IOMMU_REG rd_iommu_reg_
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typedef struct {
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td_u32 pt_sec_addr;
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td_u32 pt_sec_err_rd_addr;
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td_u32 pt_sec_err_wt_addr;
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td_u32 pt_no_sec_addr;
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td_u32 pt_no_sec_err_rd_addr;
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td_u32 pt_no_sec_err_wt_addr;
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} dmcu_iommu_pt_addr;
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typedef struct {
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osal_spinlock spin_lock;
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td_u8 *comm_base_reg;
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td_u8 *master_base_reg;
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dmcu_iommu_pt_addr pt_addr;
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} iommu_ctx;
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td_s32 dmcu_iommu_init(const dmcu_iommu_pt_addr *pt_addr);
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td_s32 dmcu_iommu_deinit(td_void);
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td_s32 dmcu_iommu_flush_tlb(td_bool flush_cache);
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void dmcu_flush_d_cache_by_all(void);
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td_void dmcu_hal_set_uart_pinmux(td_void);
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#endif
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