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/*
* Copyright (c) Hisilicon Technologies Co., Ltd. 2012-2019. All rights reserved.
* Description: decoder
* Author: Hisilicon
* Create: 2012-04-22
*/
#ifndef __DMCU_PMP_H__
#define __DMCU_PMP_H__
#include "td_type.h"
#include "soc_osal.h"
#define DMCU_MIN_PMP_ADDR 0
#define DMCU_MAX_PMP_ADDR 0xFFFFFFFF /* 4GB */
extern td_u32 __itcm_text_start;
extern td_u32 __itcm_text_load_start;
extern td_u32 __itcm_size;
typedef enum {
DMCU_REGION_MMZ_START = 0,
/* LOS REGION CFG */
DMCU_REGION_LOS_CODE_START = DMCU_REGION_MMZ_START, /* 0 */
DMCU_REGION_LOS_CODE_END, /* 1 */
DMCU_REGION_LOS_DATA_END, /* 2 */
/* PAGE_TABLE CONFIG */
DMCU_REGION_IOMMU_PT_NS, /* 3 */
/* ITCM CONFIG */
DMCU_REGION_ITCM, /* 4 */
DMCU_REGION_LOG, /* 5 */
DMCU_REGION_IPCM, /* 6 */
DMCU_REGION_MMZ_END = 9,
/*
DMCU MMU REGION CFG:
NC -- NON-CACHABLE
C -- CACHABLE
NS -- NON-SECURE
S -- SECURE
*/
DMCU_REGION_MMU_START = DMCU_REGION_MMZ_END,
DMCU_REGION_IOMMU_NS_NC_START = DMCU_REGION_MMU_START, /* 9 */
DMCU_REGION_IOMMU_NS_NC_END, /* 10 */
DMCU_REGION_IOMMU_NS_C_END, /* 11 */
DMCU_REGION_IOMMU_S_NC_END, /* 12 */
DMCU_REGION_IOMMU_S_C_END, /* 13 */
DMCU_REGION_PT_TABLE_START, /* 14 */
DMCU_REGION_MMU_END,
} dmcu_mpu_region_num;
td_s32 dmcu_pmp_region_config(void);
void dmcu_pmp_region_init(void);
void dmcu_pmp_init(void);
td_void dmcu_itcm_resume(td_void);
#endif