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159 lines
5.0 KiB
159 lines
5.0 KiB
Performance Monitoring Unit
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===========================
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The Performance Monitoring Unit (PMU) allows recording of architectural and
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microarchitectural events for profiling purposes.
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This document gives an overview of the PMU counter configuration to assist with
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implementation and to complement the PMU security guidelines given in the
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:ref:`Secure Development Guidelines` document.
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.. note::
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This section applies to Armv8-A implementations which have version 3
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of the Performance Monitors Extension (PMUv3).
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PMU Counters
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------------
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The PMU makes 32 counters available at all privilege levels:
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- 31 programmable event counters: ``PMEVCNTR<n>``, where ``n`` is ``0`` to
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``30``.
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- A dedicated cycle counter: ``PMCCNTR``.
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Architectural mappings
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~~~~~~~~~~~~~~~~~~~~~~
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+--------------+---------+----------------------------+
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| Counters | State | System Register Name |
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+==============+=========+============================+
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| | AArch64 | ``PMEVCNTR<n>_EL0[63*:0]`` |
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| Programmable +---------+----------------------------+
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| | AArch32 | ``PMEVCNTR<n>[31:0]`` |
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+--------------+---------+----------------------------+
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| | AArch64 | ``PMCCNTR_EL0[63:0]`` |
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| Cycle +---------+----------------------------+
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| | AArch32 | ``PMCCNTR[63:0]`` |
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+--------------+---------+----------------------------+
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.. note::
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Bits [63:32] are only available if ARMv8.5-PMU is implemented. Refer to the
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`Arm ARM`_ for a detailed description of ARMv8.5-PMU features.
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Configuring the PMU for counting events
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---------------------------------------
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Each programmable counter has an associated register, ``PMEVTYPER<n>`` which
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configures it. The cycle counter has the ``PMCCFILTR_EL0`` register, which has
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an identical function and bit field layout as ``PMEVTYPER<n>``. In addition,
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the counters are enabled (permitted to increment) via the ``PMCNTENSET`` and
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``PMCR`` registers. These can be accessed at all privilege levels.
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Architectural mappings
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~~~~~~~~~~~~~~~~~~~~~~
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+-----------------------------+------------------------+
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| AArch64 | AArch32 |
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+=============================+========================+
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| ``PMEVTYPER<n>_EL0[63*:0]`` | ``PMEVTYPER<n>[31:0]`` |
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+-----------------------------+------------------------+
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| ``PMCCFILTR_EL0[63*:0]`` | ``PMCCFILTR[31:0]`` |
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+-----------------------------+------------------------+
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| ``PMCNTENSET_EL0[63*:0]`` | ``PMCNTENSET[31:0]`` |
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+-----------------------------+------------------------+
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| ``PMCR_EL0[63*:0]`` | ``PMCR[31:0]`` |
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+-----------------------------+------------------------+
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.. note::
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Bits [63:32] are reserved.
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Relevant register fields
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~~~~~~~~~~~~~~~~~~~~~~~~
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For ``PMEVTYPER<n>_EL0``/``PMEVTYPER<n>`` and ``PMCCFILTR_EL0/PMCCFILTR``, the
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most important fields are:
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- ``P``:
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- Bit 31.
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- If set to ``0``, will increment the associated ``PMEVCNTR<n>`` at EL1.
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- ``NSK``:
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- Bit 29.
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- If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
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Non-secure EL1.
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- Reserved if EL3 not implemented.
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- ``NSH``:
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- Bit 27.
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- If set to ``1``, will increment the associated ``PMEVCNTR<n>`` at EL2.
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- Reserved if EL2 not implemented.
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- ``SH``:
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- Bit 24.
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- If different to the ``NSH`` bit it enables the associated ``PMEVCNTR<n>``
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at Secure EL2.
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- Reserved if Secure EL2 not implemented.
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- ``M``:
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- Bit 26.
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- If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
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EL3.
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- ``evtCount[15:10]``:
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- Extension to ``evtCount[9:0]``. Reserved unless ARMv8.1-PMU implemented.
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- ``evtCount[9:0]``:
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- The event number that the associated ``PMEVCNTR<n>`` will count.
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For ``PMCNTENSET_EL0``/``PMCNTENSET``, the most important fields are:
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- ``P[30:0]``:
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- Setting bit ``P[n]`` to ``1`` enables counter ``PMEVCNTR<n>``.
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- The effects of ``PMEVTYPER<n>`` are applied on top of this.
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In other words, the counter will not increment at any privilege level or
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security state unless it is enabled here.
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- ``C``:
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- Bit 31.
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- If set to ``1`` enables the cycle counter ``PMCCNTR``.
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For ``PMCR``/``PMCR_EL0``, the most important fields are:
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- ``DP``:
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- Bit 5.
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- If set to ``1`` it disables the cycle counter ``PMCCNTR`` where event
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counting (by ``PMEVCNTR<n>``) is prohibited (e.g. EL2 and the Secure
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world).
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- If set to ``0``, ``PMCCNTR`` will not be affected by this bit and
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therefore will be able to count where the programmable counters are
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prohibited.
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- ``E``:
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- Bit 0.
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- Enables/disables counting altogether.
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- The effects of ``PMCNTENSET`` and ``PMCR.DP`` are applied on top of this.
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In other words, if this bit is ``0`` then no counters will increment
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regardless of how the other PMU system registers or bit fields are
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configured.
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.. rubric:: References
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- `Arm ARM`_
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--------------
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*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.*
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.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest
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