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259 lines
6.4 KiB
259 lines
6.4 KiB
/*
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* Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stdint.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/st/etzpc.h>
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#include <dt-bindings/soc/st,stm32-etzpc.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <libfdt.h>
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#include <platform_def.h>
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/* Device Tree related definitions */
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#define ETZPC_COMPAT "st,stm32-etzpc"
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#define ETZPC_LOCK_MASK 0x1U
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#define ETZPC_MODE_SHIFT 8
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#define ETZPC_MODE_MASK GENMASK(1, 0)
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#define ETZPC_ID_SHIFT 16
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#define ETZPC_ID_MASK GENMASK(7, 0)
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/* ID Registers */
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#define ETZPC_TZMA0_SIZE 0x000U
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#define ETZPC_DECPROT0 0x010U
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#define ETZPC_DECPROT_LOCK0 0x030U
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#define ETZPC_HWCFGR 0x3F0U
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#define ETZPC_VERR 0x3F4U
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/* ID Registers fields */
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#define ETZPC_TZMA0_SIZE_LOCK BIT(31)
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#define ETZPC_DECPROT0_MASK GENMASK(1, 0)
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#define ETZPC_HWCFGR_NUM_TZMA_SHIFT 0
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#define ETZPC_HWCFGR_NUM_PER_SEC_SHIFT 8
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#define ETZPC_HWCFGR_NUM_AHB_SEC_SHIFT 16
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#define ETZPC_HWCFGR_CHUNCKS1N4_SHIFT 24
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#define DECPROT_SHIFT 1
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#define IDS_PER_DECPROT_REGS 16U
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#define IDS_PER_DECPROT_LOCK_REGS 32U
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/*
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* etzpc_instance.
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* base : register base address set during init given by user
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* chunk_size : supported TZMA size steps
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* num_tzma: number of TZMA zone read from register at init
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* num_ahb_sec : number of securable AHB master zone read from register
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* num_per_sec : number of securable AHB & APB Peripherals read from register
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* revision : IP revision read from register at init
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*/
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struct etzpc_instance {
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uintptr_t base;
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uint8_t chunck_size;
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uint8_t num_tzma;
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uint8_t num_per_sec;
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uint8_t num_ahb_sec;
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uint8_t revision;
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};
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/* Only 1 instance of the ETZPC is expected per platform */
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static struct etzpc_instance etzpc_dev;
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/*
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* Implementation uses uint8_t to store each securable DECPROT configuration.
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* When resuming from deep suspend, the DECPROT configurations are restored.
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*/
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#define PERIPH_LOCK_BIT BIT(7)
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#define PERIPH_ATTR_MASK GENMASK(2, 0)
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#if ENABLE_ASSERTIONS
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static bool valid_decprot_id(unsigned int id)
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{
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return id < (unsigned int)etzpc_dev.num_per_sec;
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}
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static bool valid_tzma_id(unsigned int id)
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{
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return id < (unsigned int)etzpc_dev.num_tzma;
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}
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#endif
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/*
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* etzpc_configure_decprot : Load a DECPROT configuration
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* decprot_id : ID of the IP
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* decprot_attr : Restriction access attribute
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*/
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void etzpc_configure_decprot(uint32_t decprot_id,
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enum etzpc_decprot_attributes decprot_attr)
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{
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uintptr_t offset = 4U * (decprot_id / IDS_PER_DECPROT_REGS);
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uint32_t shift = (decprot_id % IDS_PER_DECPROT_REGS) << DECPROT_SHIFT;
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uint32_t masked_decprot = (uint32_t)decprot_attr & ETZPC_DECPROT0_MASK;
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assert(valid_decprot_id(decprot_id));
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mmio_clrsetbits_32(etzpc_dev.base + ETZPC_DECPROT0 + offset,
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(uint32_t)ETZPC_DECPROT0_MASK << shift,
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masked_decprot << shift);
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}
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/*
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* etzpc_get_decprot : Get the DECPROT attribute
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* decprot_id : ID of the IP
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* return : Attribute of this DECPROT
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*/
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enum etzpc_decprot_attributes etzpc_get_decprot(uint32_t decprot_id)
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{
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uintptr_t offset = 4U * (decprot_id / IDS_PER_DECPROT_REGS);
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uint32_t shift = (decprot_id % IDS_PER_DECPROT_REGS) << DECPROT_SHIFT;
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uintptr_t base_decprot = etzpc_dev.base + offset;
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uint32_t value;
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assert(valid_decprot_id(decprot_id));
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value = (mmio_read_32(base_decprot + ETZPC_DECPROT0) >> shift) &
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ETZPC_DECPROT0_MASK;
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return (enum etzpc_decprot_attributes)value;
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}
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/*
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* etzpc_lock_decprot : Lock access to the DECPROT attribute
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* decprot_id : ID of the IP
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*/
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void etzpc_lock_decprot(uint32_t decprot_id)
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{
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uintptr_t offset = 4U * (decprot_id / IDS_PER_DECPROT_LOCK_REGS);
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uint32_t shift = BIT(decprot_id % IDS_PER_DECPROT_LOCK_REGS);
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uintptr_t base_decprot = etzpc_dev.base + offset;
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assert(valid_decprot_id(decprot_id));
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mmio_write_32(base_decprot + ETZPC_DECPROT_LOCK0, shift);
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}
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/*
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* etzpc_configure_tzma : Configure the target TZMA read only size
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* tzma_id : ID of the memory
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* tzma_value : read-only size
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*/
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void etzpc_configure_tzma(uint32_t tzma_id, uint16_t tzma_value)
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{
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assert(valid_tzma_id(tzma_id));
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mmio_write_32(etzpc_dev.base + ETZPC_TZMA0_SIZE +
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(sizeof(uint32_t) * tzma_id), tzma_value);
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}
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/*
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* etzpc_get_tzma : Get the target TZMA read only size
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* tzma_id : TZMA ID
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* return : Size of read only size
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*/
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uint16_t etzpc_get_tzma(uint32_t tzma_id)
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{
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assert(valid_tzma_id(tzma_id));
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return (uint16_t)mmio_read_32(etzpc_dev.base + ETZPC_TZMA0_SIZE +
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(sizeof(uint32_t) * tzma_id));
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}
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/*
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* etzpc_lock_tzma : Lock the target TZMA
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* tzma_id : TZMA ID
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*/
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void etzpc_lock_tzma(uint32_t tzma_id)
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{
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assert(valid_tzma_id(tzma_id));
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mmio_setbits_32(etzpc_dev.base + ETZPC_TZMA0_SIZE +
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(sizeof(uint32_t) * tzma_id), ETZPC_TZMA0_SIZE_LOCK);
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}
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/*
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* etzpc_get_lock_tzma : Return the lock status of the target TZMA
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* tzma_id : TZMA ID
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* return : True if TZMA is locked, false otherwise
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*/
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bool etzpc_get_lock_tzma(uint32_t tzma_id)
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{
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uint32_t tzma_size;
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assert(valid_tzma_id(tzma_id));
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tzma_size = mmio_read_32(etzpc_dev.base + ETZPC_TZMA0_SIZE +
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(sizeof(uint32_t) * tzma_id));
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return (tzma_size & ETZPC_TZMA0_SIZE_LOCK) != 0;
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}
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/*
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* etzpc_get_num_per_sec : Return the DECPROT ID limit value
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*/
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uint8_t etzpc_get_num_per_sec(void)
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{
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return etzpc_dev.num_per_sec;
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}
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/*
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* etzpc_get_revision : Return the ETZPC IP revision
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*/
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uint8_t etzpc_get_revision(void)
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{
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return etzpc_dev.revision;
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}
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/*
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* etzpc_get_base_address : Return the ETZPC IP base address
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*/
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uintptr_t etzpc_get_base_address(void)
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{
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return etzpc_dev.base;
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}
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/*
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* etzpc_init : Initialize the ETZPC driver
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* Return 0 on success and a negative errno on failure
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*/
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int etzpc_init(void)
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{
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uint32_t hwcfg;
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int node;
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struct dt_node_info etzpc_info;
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node = dt_get_node(&etzpc_info, -1, ETZPC_COMPAT);
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if (node < 0) {
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return -EIO;
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}
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/* Check ETZPC is secure only */
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if (etzpc_info.status != DT_SECURE) {
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return -EACCES;
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}
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etzpc_dev.base = etzpc_info.base;
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hwcfg = mmio_read_32(etzpc_dev.base + ETZPC_HWCFGR);
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etzpc_dev.num_tzma = (uint8_t)(hwcfg >> ETZPC_HWCFGR_NUM_TZMA_SHIFT);
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etzpc_dev.num_per_sec = (uint8_t)(hwcfg >>
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ETZPC_HWCFGR_NUM_PER_SEC_SHIFT);
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etzpc_dev.num_ahb_sec = (uint8_t)(hwcfg >>
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ETZPC_HWCFGR_NUM_AHB_SEC_SHIFT);
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etzpc_dev.chunck_size = (uint8_t)(hwcfg >>
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ETZPC_HWCFGR_CHUNCKS1N4_SHIFT);
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etzpc_dev.revision = mmio_read_8(etzpc_dev.base + ETZPC_VERR);
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VERBOSE("ETZPC version 0x%x", etzpc_dev.revision);
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return 0;
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}
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