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341 lines
9.6 KiB
341 lines
9.6 KiB
#
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# Copyright (c) 2016-2021, ARM Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Default, static values for build variables, listed in alphabetic order.
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# Dependencies between build options, if any, are handled in the top-level
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# Makefile, after this file is included. This ensures that the former is better
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# poised to handle dependencies, as all build variables would have a default
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# value by then.
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# Use T32 by default
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AARCH32_INSTRUCTION_SET := T32
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# The AArch32 Secure Payload to be built as BL32 image
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AARCH32_SP := none
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# The Target build architecture. Supported values are: aarch64, aarch32.
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ARCH := aarch64
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# ARM Architecture feature modifiers: none by default
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ARM_ARCH_FEATURE := none
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# ARM Architecture major and minor versions: 8.0 by default.
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ARM_ARCH_MAJOR := 8
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ARM_ARCH_MINOR := 0
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# Base commit to perform code check on
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BASE_COMMIT := origin/master
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# Execute BL2 at EL3
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BL2_AT_EL3 := 0
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# BL2 image is stored in XIP memory, for now, this option is only supported
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# when BL2_AT_EL3 is 1.
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BL2_IN_XIP_MEM := 0
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# Do dcache invalidate upon BL2 entry at EL3
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BL2_INV_DCACHE := 1
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# Select the branch protection features to use.
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BRANCH_PROTECTION := 0
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# By default, consider that the platform may release several CPUs out of reset.
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# The platform Makefile is free to override this value.
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COLD_BOOT_SINGLE_CPU := 0
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# Flag to compile in coreboot support code. Exclude by default. The coreboot
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# Makefile system will set this when compiling TF as part of a coreboot image.
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COREBOOT := 0
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# For Chain of Trust
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CREATE_KEYS := 1
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# Build flag to include AArch32 registers in cpu context save and restore during
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# world switch. This flag must be set to 0 for AArch64-only platforms.
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CTX_INCLUDE_AARCH32_REGS := 1
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# Include FP registers in cpu context
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CTX_INCLUDE_FPREGS := 0
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# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
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# must be set to 1 if the platform wants to use this feature in the Secure
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# world. It is not needed to use it in the Non-secure world.
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CTX_INCLUDE_PAUTH_REGS := 0
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# Include Nested virtualization control (Armv8.4-NV) registers in cpu context.
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# This must be set to 1 if architecture implements Nested Virtualization
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# Extension and platform wants to use this feature in the Secure world
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CTX_INCLUDE_NEVE_REGS := 0
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# Debug build
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DEBUG := 0
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# By default disable authenticated decryption support.
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DECRYPTION_SUPPORT := none
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# Build platform
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DEFAULT_PLAT := fvp
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# Disable the generation of the binary image (ELF only).
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DISABLE_BIN_GENERATION := 0
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# Disable MTPMU if FEAT_MTPMU is supported. Default is 0 to keep backwards
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# compatibility.
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DISABLE_MTPMU := 0
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# Enable capability to disable authentication dynamically. Only meant for
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# development platforms.
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DYN_DISABLE_AUTH := 0
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# Build option to enable MPAM for lower ELs
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ENABLE_MPAM_FOR_LOWER_ELS := 0
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# Flag to Enable Position Independant support (PIE)
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ENABLE_PIE := 0
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# Flag to enable Performance Measurement Framework
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ENABLE_PMF := 0
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# Flag to enable PSCI STATs functionality
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ENABLE_PSCI_STAT := 0
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# Flag to enable runtime instrumentation using PMF
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ENABLE_RUNTIME_INSTRUMENTATION := 0
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# Flag to enable stack corruption protection
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ENABLE_STACK_PROTECTOR := 0
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# Flag to enable exception handling in EL3
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EL3_EXCEPTION_HANDLING := 0
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# Flag to enable Branch Target Identification.
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# Internal flag not meant for direct setting.
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# Use BRANCH_PROTECTION to enable BTI.
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ENABLE_BTI := 0
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# Flag to enable Pointer Authentication.
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# Internal flag not meant for direct setting.
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# Use BRANCH_PROTECTION to enable PAUTH.
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ENABLE_PAUTH := 0
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# By default BL31 encryption disabled
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ENCRYPT_BL31 := 0
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# By default BL32 encryption disabled
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ENCRYPT_BL32 := 0
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# Default dummy firmware encryption key
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ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef
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# Default dummy nonce for firmware encryption
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ENC_NONCE := 1234567890abcdef12345678
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# Build flag to treat usage of deprecated platform and framework APIs as error.
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ERROR_DEPRECATED := 0
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# Fault injection support
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FAULT_INJECTION_SUPPORT := 0
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# Byte alignment that each component in FIP is aligned to
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FIP_ALIGN := 0
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# Default FIP file name
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FIP_NAME := fip.bin
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# Default FWU_FIP file name
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FWU_FIP_NAME := fwu_fip.bin
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# By default firmware encryption with SSK
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FW_ENC_STATUS := 0
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# For Chain of Trust
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GENERATE_COT := 0
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# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
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# default, they are for Secure EL1.
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GICV2_G0_FOR_EL3 := 0
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# Route External Aborts to EL3. Disabled by default; External Aborts are handled
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# by lower ELs.
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HANDLE_EA_EL3_FIRST := 0
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# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512.
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# The default value is sha256.
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HASH_ALG := sha256
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# Whether system coherency is managed in hardware, without explicit software
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# operations.
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HW_ASSISTED_COHERENCY := 0
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# Set the default algorithm for the generation of Trusted Board Boot keys
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KEY_ALG := rsa
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# Set the default key size in case KEY_ALG is rsa
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ifeq ($(KEY_ALG),rsa)
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KEY_SIZE := 2048
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endif
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# Option to build TF with Measured Boot support
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MEASURED_BOOT := 0
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# NS timer register save and restore
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NS_TIMER_SWITCH := 0
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# Include lib/libc in the final image
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OVERRIDE_LIBC := 0
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# Build PL011 UART driver in minimal generic UART mode
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PL011_GENERIC_UART := 0
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# By default, consider that the platform's reset address is not programmable.
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# The platform Makefile is free to override this value.
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PROGRAMMABLE_RESET_ADDRESS := 0
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# Flag used to choose the power state format: Extended State-ID or Original
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PSCI_EXTENDED_STATE_ID := 0
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# Enable RAS support
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RAS_EXTENSION := 0
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# By default, BL1 acts as the reset handler, not BL31
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RESET_TO_BL31 := 0
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# For Chain of Trust
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SAVE_KEYS := 0
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# Software Delegated Exception support
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SDEI_SUPPORT := 0
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# True Random Number firmware Interface
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TRNG_SUPPORT := 0
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# Whether code and read-only data should be put on separate memory pages. The
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# platform Makefile is free to override this value.
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SEPARATE_CODE_AND_RODATA := 0
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# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a
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# separate memory region, which may be discontiguous from the rest of BL31.
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SEPARATE_NOBITS_REGION := 0
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# If the BL31 image initialisation code is recalimed after use for the secondary
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# cores stack
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RECLAIM_INIT_CODE := 0
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# SPD choice
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SPD := none
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# Enable the Management Mode (MM)-based Secure Partition Manager implementation
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SPM_MM := 0
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# Use SPM at S-EL2 as a default config for SPMD
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SPMD_SPM_AT_SEL2 := 1
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# Flag to introduce an infinite loop in BL1 just before it exits into the next
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# image. This is meant to help debugging the post-BL2 phase.
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SPIN_ON_BL1_EXIT := 0
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# Flags to build TF with Trusted Boot support
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TRUSTED_BOARD_BOOT := 0
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# Build option to choose whether Trusted Firmware uses Coherent memory or not.
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USE_COHERENT_MEM := 1
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# Build option to add debugfs support
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USE_DEBUGFS := 0
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# Build option to fconf based io
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ARM_IO_IN_DTB := 0
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# Build option to support SDEI through fconf
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SDEI_IN_FCONF := 0
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# Build option to support Secure Interrupt descriptors through fconf
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SEC_INT_DESC_IN_FCONF := 0
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# Build option to choose whether Trusted Firmware uses library at ROM
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USE_ROMLIB := 0
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# Build option to choose whether the xlat tables of BL images can be read-only.
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# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES,
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# which is the per BL-image option that actually enables the read-only tables
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# API. The reason for having this additional option is to have a common high
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# level makefile where we can check for incompatible features/build options.
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ALLOW_RO_XLAT_TABLES := 0
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# Chain of trust.
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COT := tbbr
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# Use tbbr_oid.h instead of platform_oid.h
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USE_TBBR_DEFS := 1
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# Build verbosity
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V := 0
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# Whether to enable D-Cache early during warm boot. This is usually
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# applicable for platforms wherein interconnect programming is not
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# required to enable cache coherency after warm reset (eg: single cluster
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# platforms).
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WARMBOOT_ENABLE_DCACHE_EARLY := 0
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# Build option to enable/disable the Statistical Profiling Extensions
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ENABLE_SPE_FOR_LOWER_ELS := 1
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# SPE is only supported on AArch64 so disable it on AArch32.
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ifeq (${ARCH},aarch32)
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override ENABLE_SPE_FOR_LOWER_ELS := 0
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endif
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# Include Memory Tagging Extension registers in cpu context. This must be set
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# to 1 if the platform wants to use this feature in the Secure world and MTE is
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# enabled at ELX.
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CTX_INCLUDE_MTE_REGS := 0
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ENABLE_AMU := 0
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# By default, enable Scalable Vector Extension if implemented for Non-secure
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# lower ELs
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# Note SVE is only supported on AArch64 - therefore do not enable in AArch32
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ifneq (${ARCH},aarch32)
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ENABLE_SVE_FOR_NS := 1
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else
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override ENABLE_SVE_FOR_NS := 0
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endif
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SANITIZE_UB := off
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# For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock
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# implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
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# Default: disabled
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USE_SPINLOCK_CAS := 0
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# Enable Link Time Optimization
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ENABLE_LTO := 0
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# Build flag to include EL2 registers in cpu context save and restore during
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# S-EL2 firmware entry/exit. This flag is to be used with SPD=spmd option.
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# Default is 0.
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CTX_INCLUDE_EL2_REGS := 0
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# Enable Memory tag extension which is supported for architecture greater
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# than Armv8.5-A
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# By default it is set to "no"
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SUPPORT_STACK_MEMTAG := no
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# Select workaround for AT speculative behaviour.
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ERRATA_SPECULATIVE_AT := 0
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# Trap RAS error record access from lower EL
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RAS_TRAP_LOWER_EL_ERR_ACCESS := 0
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# Build option to create cot descriptors using fconf
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COT_DESC_IN_DTB := 0
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# Build option to provide openssl directory path
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OPENSSL_DIR := /usr
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# Build option to use the SP804 timer instead of the generic one
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USE_SP804_TIMER := 0
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