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123 lines
3.3 KiB
123 lines
3.3 KiB
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef HIKEY_LAYOUT_H
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#define HIKEY_LAYOUT_H
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/*
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* Platform memory map related constants
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*/
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#define XG2RAM0_BASE 0xF9800000
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#define XG2RAM0_SIZE 0x00400000
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/*
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* BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
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*/
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#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
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#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
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#define BL1_XG2RAM0_OFFSET 0x1000
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/*
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* BL1 specific defines.
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*
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* Both loader and BL1_RO region stay in SRAM since they are used to simulate
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* ROM.
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* Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
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*
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* ++++++++++ 0xF980_0000
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* + loader +
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* ++++++++++ 0xF980_1000
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* + BL1_RO +
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* ++++++++++ 0xF981_8000
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* + BL1_RW +
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* ++++++++++ 0xF989_8000
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*/
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#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET)
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#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x18000)
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#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_8000 */
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#define BL1_RW_SIZE (0x00080000)
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#define BL1_RW_LIMIT (0xF9898000)
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/*
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* Non-Secure BL1U specific defines.
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*/
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#define NS_BL1U_BASE (0xf9828000)
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#define NS_BL1U_SIZE (0x00010000)
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#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
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/*
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* BL2 specific defines.
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*
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* Both loader and BL2 region stay in SRAM.
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* Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
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*
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* ++++++++++ 0xF980_0000
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* + loader +
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* ++++++++++ 0xF980_1000
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* + BL2 +
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* ++++++++++ 0xF983_0000
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*/
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#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */
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#define BL2_LIMIT (0xF9830000) /* 0xf983_0000 */
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/*
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* SCP_BL2 specific defines.
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* In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer
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* at 0x0100_0000. Then BL2 will parse the sections and loaded them into
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* predefined separated buffers.
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*/
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#define SCP_BL2_BASE (DDR_BASE + 0x01000000)
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#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000)
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#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE)
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/*
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* BL31 specific defines.
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*/
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#define BL31_BASE (0xF9858000) /* 0xf985_8000 */
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#define BL31_LIMIT (0xF9898000)
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/*
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* BL3-2 specific defines.
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*/
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/*
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* The TSP currently executes from TZC secured area of DRAM or SRAM.
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*/
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#define BL32_SRAM_BASE BL31_LIMIT
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#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
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#define BL32_DRAM_BASE DDR_SEC_BASE
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#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
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#ifdef SPD_opteed
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/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
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#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
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#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
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#endif
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#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
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#define BL32_BASE BL32_DRAM_BASE
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#define BL32_LIMIT BL32_DRAM_LIMIT
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#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
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#define BL32_BASE BL32_SRAM_BASE
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#define BL32_LIMIT BL32_SRAM_LIMIT
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#else
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#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
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#endif
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/* BL32 is mandatory in AArch32 */
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#ifdef __aarch64__
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#ifdef SPD_none
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#undef BL32_BASE
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#endif /* SPD_none */
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#endif
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#endif /* HIKEY_LAYOUT_H */
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