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180 lines
6.4 KiB
180 lines
6.4 KiB
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef HI3660_CRG_H
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#define HI3660_CRG_H
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#define CRG_REG_BASE 0xFFF35000
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#define CRG_PEREN0_REG (CRG_REG_BASE + 0x000)
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#define CRG_PERDIS0_REG (CRG_REG_BASE + 0x004)
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#define CRG_PERSTAT0_REG (CRG_REG_BASE + 0x008)
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#define PEREN0_GT_CLK_AOMM (1U << 31)
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#define CRG_PEREN1_REG (CRG_REG_BASE + 0x010)
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#define CRG_PERDIS1_REG (CRG_REG_BASE + 0x014)
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#define CRG_PERSTAT1_REG (CRG_REG_BASE + 0x018)
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#define CRG_PEREN2_REG (CRG_REG_BASE + 0x020)
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#define CRG_PERDIS2_REG (CRG_REG_BASE + 0x024)
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#define CRG_PERSTAT2_REG (CRG_REG_BASE + 0x028)
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#define PEREN2_HKADCSSI (1 << 24)
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#define CRG_PEREN3_REG (CRG_REG_BASE + 0x030)
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#define CRG_PERDIS3_REG (CRG_REG_BASE + 0x034)
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#define CRG_PEREN4_REG (CRG_REG_BASE + 0x040)
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#define CRG_PERDIS4_REG (CRG_REG_BASE + 0x044)
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#define CRG_PERCLKEN4_REG (CRG_REG_BASE + 0x048)
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#define CRG_PERSTAT4_REG (CRG_REG_BASE + 0x04C)
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#define GT_ACLK_USB3OTG (1 << 1)
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#define GT_CLK_USB3OTG_REF (1 << 0)
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#define CRG_PEREN5_REG (CRG_REG_BASE + 0x050)
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#define CRG_PERDIS5_REG (CRG_REG_BASE + 0x054)
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#define CRG_PERSTAT5_REG (CRG_REG_BASE + 0x058)
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#define CRG_PERRSTEN0_REG (CRG_REG_BASE + 0x060)
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#define CRG_PERRSTDIS0_REG (CRG_REG_BASE + 0x064)
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#define CRG_PERRSTSTAT0_REG (CRG_REG_BASE + 0x068)
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#define CRG_PERRSTEN1_REG (CRG_REG_BASE + 0x06C)
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#define CRG_PERRSTDIS1_REG (CRG_REG_BASE + 0x070)
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#define CRG_PERRSTSTAT1_REG (CRG_REG_BASE + 0x074)
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#define CRG_PERRSTEN2_REG (CRG_REG_BASE + 0x078)
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#define CRG_PERRSTDIS2_REG (CRG_REG_BASE + 0x07C)
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#define CRG_PERRSTSTAT2_REG (CRG_REG_BASE + 0x080)
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#define PERRSTEN2_HKADCSSI (1 << 24)
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#define CRG_PERRSTEN3_REG (CRG_REG_BASE + 0x084)
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#define CRG_PERRSTDIS3_REG (CRG_REG_BASE + 0x088)
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#define CRG_PERRSTSTAT3_REG (CRG_REG_BASE + 0x08C)
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#define CRG_PERRSTEN4_REG (CRG_REG_BASE + 0x090)
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#define CRG_PERRSTDIS4_REG (CRG_REG_BASE + 0x094)
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#define CRG_PERRSTSTAT4_REG (CRG_REG_BASE + 0x098)
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#define IP_RST_USB3OTG_MUX (1 << 8)
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#define IP_RST_USB3OTG_AHBIF (1 << 7)
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#define IP_RST_USB3OTG_32K (1 << 6)
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#define IP_RST_USB3OTG (1 << 5)
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#define IP_RST_USB3OTGPHY_POR (1 << 3)
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#define CRG_PERRSTEN5_REG (CRG_REG_BASE + 0x09C)
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#define CRG_PERRSTDIS5_REG (CRG_REG_BASE + 0x0A0)
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#define CRG_PERRSTSTAT5_REG (CRG_REG_BASE + 0x0A4)
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/* bit fields in CRG_PERI */
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#define PERI_PCLK_PCTRL_BIT (1U << 31)
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#define PERI_TIMER12_BIT (1 << 25)
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#define PERI_TIMER11_BIT (1 << 24)
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#define PERI_TIMER10_BIT (1 << 23)
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#define PERI_TIMER9_BIT (1 << 22)
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#define PERI_UART5_BIT (1 << 15)
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#define PERI_UFS_BIT (1 << 12)
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#define PERI_ARST_UFS_BIT (1 << 7)
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#define PERI_PPLL2_EN_CPU (1 << 3)
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#define PERI_PWM_BIT (1 << 0)
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#define PERI_DDRC_BIT (1 << 0)
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#define PERI_DDRC_D_BIT (1 << 4)
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#define PERI_DDRC_C_BIT (1 << 3)
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#define PERI_DDRC_B_BIT (1 << 2)
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#define PERI_DDRC_A_BIT (1 << 1)
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#define PERI_DDRC_DMUX_BIT (1 << 0)
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#define CRG_CLKDIV0_REG (CRG_REG_BASE + 0x0A0)
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#define SC_DIV_LPMCU_MASK ((0x1F << 5) << 16)
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#define SC_DIV_LPMCU(x) (((x) & 0x1F) << 5)
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#define CRG_CLKDIV1_REG (CRG_REG_BASE + 0x0B0)
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#define SEL_LPMCU_PLL_MASK ((1 << 1) << 16)
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#define SEL_SYSBUS_MASK ((1 << 0) << 16)
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#define SEL_LPMCU_PLL1 (1 << 1)
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#define SEL_LPMCU_PLL0 (0 << 1)
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#define SEL_SYSBUS_PLL0 (1 << 0)
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#define SEL_SYSBUS_PLL1 (0 << 0)
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#define CRG_CLKDIV3_REG (CRG_REG_BASE + 0x0B4)
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#define CRG_CLKDIV5_REG (CRG_REG_BASE + 0x0BC)
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#define CRG_CLKDIV8_REG (CRG_REG_BASE + 0x0C8)
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#define CRG_CLKDIV12_REG (CRG_REG_BASE + 0x0D8)
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#define SC_DIV_A53HPM_MASK (0x7 << 13)
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#define SC_DIV_A53HPM(x) (((x) & 0x7) << 13)
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#define CRG_CLKDIV16_REG (CRG_REG_BASE + 0x0E8)
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#define DDRC_CLK_SW_REQ_CFG_MASK (0x3 << 12)
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#define DDRC_CLK_SW_REQ_CFG(x) (((x) & 0x3) << 12)
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#define SC_DIV_UFSPHY_CFG_MASK (0x3 << 9)
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#define SC_DIV_UFSPHY_CFG(x) (((x) & 0x3) << 9)
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#define DDRCPLL_SW (1 << 8)
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#define CRG_CLKDIV17_REG (CRG_REG_BASE + 0x0EC)
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#define SC_DIV_UFS_PERIBUS (1 << 14)
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#define CRG_CLKDIV18_REG (CRG_REG_BASE + 0x0F0)
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#define CRG_CLKDIV19_REG (CRG_REG_BASE + 0x0F4)
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#define CRG_CLKDIV20_REG (CRG_REG_BASE + 0x0F8)
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#define CLKDIV20_GT_CLK_AOMM (1 << 3)
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#define CRG_CLKDIV22_REG (CRG_REG_BASE + 0x100)
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#define SEL_PLL_320M_MASK (1 << 16)
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#define SEL_PLL2_320M (1 << 0)
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#define SEL_PLL0_320M (0 << 0)
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#define CRG_CLKDIV23_REG (CRG_REG_BASE + 0x104)
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#define PERI_DDRC_SW_BIT (1 << 13)
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#define DIV_CLK_DDRSYS_MASK (0x3 << 10)
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#define DIV_CLK_DDRSYS(x) (((x) & 0x3) << 10)
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#define GET_DIV_CLK_DDRSYS(x) (((x) & DIV_CLK_DDRSYS_MASK) >> 10)
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#define DIV_CLK_DDRCFG_MASK (0x6 << 5)
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#define DIV_CLK_DDRCFG(x) (((x) & 0x6) << 5)
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#define GET_DIV_CLK_DDRCFG(x) (((x) & DIV_CLK_DDRCFG_MASK) >> 5)
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#define DIV_CLK_DDRC_MASK 0x1F
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#define DIV_CLK_DDRC(x) ((x) & DIV_CLK_DDRC_MASK)
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#define GET_DIV_CLK_DDRC(x) ((x) & DIV_CLK_DDRC_MASK)
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#define CRG_CLKDIV25_REG (CRG_REG_BASE + 0x10C)
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#define DIV_SYSBUS_PLL_MASK (0xF << 16)
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#define DIV_SYSBUS_PLL(x) ((x) & 0xF)
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#define CRG_PERI_CTRL2_REG (CRG_REG_BASE + 0x128)
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#define PERI_TIME_STAMP_CLK_MASK (0x7 << 28)
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#define PERI_TIME_STAMP_CLK_DIV(x) (((x) & 0x7) << 22)
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#define CRG_ISODIS_REG (CRG_REG_BASE + 0x148)
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#define CRG_PERPWREN_REG (CRG_REG_BASE + 0x150)
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#define CRG_PEREN7_REG (CRG_REG_BASE + 0x420)
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#define CRG_PERDIS7_REG (CRG_REG_BASE + 0x424)
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#define CRG_PERSTAT7_REG (CRG_REG_BASE + 0x428)
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#define GT_CLK_UFSPHY_CFG (1 << 14)
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#define CRG_PEREN8_REG (CRG_REG_BASE + 0x430)
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#define CRG_PERDIS8_REG (CRG_REG_BASE + 0x434)
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#define CRG_PERSTAT8_REG (CRG_REG_BASE + 0x438)
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#define PERI_DMC_D_BIT (1 << 22)
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#define PERI_DMC_C_BIT (1 << 21)
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#define PERI_DMC_B_BIT (1 << 20)
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#define PERI_DMC_A_BIT (1 << 19)
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#define PERI_DMC_BIT (1 << 18)
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#define CRG_PEREN11_REG (CRG_REG_BASE + 0x460)
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#define PPLL1_GATE_CPU (1 << 18)
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#define CRG_PERSTAT11_REG (CRG_REG_BASE + 0x46C)
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#define PPLL3_EN_STAT (1 << 21)
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#define PPLL2_EN_STAT (1 << 20)
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#define PPLL1_EN_STAT (1 << 19)
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#define CRG_IVP_SEC_RSTDIS_REG (CRG_REG_BASE + 0xC04)
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#define CRG_ISP_SEC_RSTDIS_REG (CRG_REG_BASE + 0xC84)
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#define CRG_RVBAR(c, n) (0xE00 + (0x10 * c) + (0x4 * n))
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#define CRG_GENERAL_SEC_RSTEN_REG (CRG_REG_BASE + 0xE20)
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#define CRG_GENERAL_SEC_RSTDIS_REG (CRG_REG_BASE + 0xE24)
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#define IP_RST_GPIO0_SEC (1 << 2)
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#define CRG_GENERAL_SEC_CLKDIV0_REG (CRG_REG_BASE + 0xE90)
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#define SC_DIV_AO_HISE_MASK 3
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#define SC_DIV_AO_HISE(x) ((x) & 0x3)
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#endif /* HI3660_CRG_H */
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