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76 lines
2.6 KiB
76 lines
2.6 KiB
#
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# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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PLAT_INCLUDES := \
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-Iplat/intel/soc/agilex/include/ \
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-Iplat/intel/soc/common/drivers/ \
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-Iplat/intel/soc/common/include/
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# Include GICv2 driver files
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include drivers/arm/gic/v2/gicv2.mk
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AGX_GICv2_SOURCES := \
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${GICV2_SOURCES} \
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plat/common/plat_gicv2.c
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PLAT_BL_COMMON_SOURCES := \
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${AGX_GICv2_SOURCES} \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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drivers/ti/uart/aarch64/16550_console.S \
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lib/xlat_tables/aarch64/xlat_tables.c \
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lib/xlat_tables/xlat_tables_common.c \
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plat/intel/soc/common/aarch64/platform_common.c \
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plat/intel/soc/common/aarch64/plat_helpers.S \
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plat/intel/soc/common/socfpga_delay_timer.c
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BL2_SOURCES += \
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common/desc_image_load.c \
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drivers/mmc/mmc.c \
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drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
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drivers/io/io_storage.c \
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drivers/io/io_block.c \
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drivers/io/io_fip.c \
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drivers/partition/partition.c \
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drivers/partition/gpt.c \
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drivers/synopsys/emmc/dw_mmc.c \
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lib/cpus/aarch64/cortex_a53.S \
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plat/intel/soc/agilex/bl2_plat_setup.c \
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plat/intel/soc/agilex/soc/agilex_clock_manager.c \
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plat/intel/soc/agilex/soc/agilex_memory_controller.c \
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plat/intel/soc/agilex/soc/agilex_mmc.c \
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plat/intel/soc/agilex/soc/agilex_pinmux.c \
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plat/intel/soc/common/bl2_plat_mem_params_desc.c \
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plat/intel/soc/common/socfpga_image_load.c \
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plat/intel/soc/common/socfpga_storage.c \
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plat/intel/soc/common/soc/socfpga_emac.c \
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plat/intel/soc/common/soc/socfpga_handoff.c \
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plat/intel/soc/common/soc/socfpga_mailbox.c \
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plat/intel/soc/common/soc/socfpga_reset_manager.c \
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plat/intel/soc/common/soc/socfpga_system_manager.c \
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plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
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plat/intel/soc/common/drivers/wdt/watchdog.c \
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plat/intel/soc/common/drivers/ccu/ncore_ccu.c
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BL31_SOURCES += \
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drivers/arm/cci/cci.c \
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lib/cpus/aarch64/aem_generic.S \
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lib/cpus/aarch64/cortex_a53.S \
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plat/common/plat_psci_common.c \
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plat/intel/soc/agilex/bl31_plat_setup.c \
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plat/intel/soc/common/socfpga_psci.c \
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plat/intel/soc/common/socfpga_sip_svc.c \
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plat/intel/soc/common/socfpga_topology.c \
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plat/intel/soc/common/soc/socfpga_mailbox.c \
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plat/intel/soc/common/soc/socfpga_reset_manager.c
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PROGRAMMABLE_RESET_ADDRESS := 0
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BL2_AT_EL3 := 1
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BL2_INV_DCACHE := 0
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MULTI_CONSOLE_API := 1
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USE_COHERENT_MEM := 1
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