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330 lines
11 KiB
330 lines
11 KiB
/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <drivers/console.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/mmio.h>
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#include <lib/psci/psci.h>
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#include <plat/common/platform.h>
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#include <memctrl.h>
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#include <pmc.h>
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#include <tegra_def.h>
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#include <tegra_platform.h>
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#include <tegra_private.h>
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extern uint64_t tegra_bl31_phys_base;
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extern uint64_t tegra_sec_entry_point;
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/*******************************************************************************
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* This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
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* call to get the `power_state` parameter. This allows the platform to encode
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* the appropriate State-ID field within the `power_state` parameter which can
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* be utilized in `pwr_domain_suspend()` to suspend to system affinity level.
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******************************************************************************/
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static void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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/* all affinities use system suspend state id */
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for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) {
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req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN;
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}
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}
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/*******************************************************************************
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* Handler called when an affinity instance is about to enter standby.
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******************************************************************************/
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static void tegra_cpu_standby(plat_local_state_t cpu_state)
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{
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u_register_t saved_scr_el3;
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(void)cpu_state;
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/* Tegra SoC specific handler */
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if (tegra_soc_cpu_standby(cpu_state) != PSCI_E_SUCCESS)
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ERROR("%s failed\n", __func__);
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saved_scr_el3 = read_scr_el3();
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/*
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* As per ARM ARM D1.17.2, any physical IRQ interrupt received by the
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* PE will be treated as a wake-up event, if SCR_EL3.IRQ is set to '1',
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* irrespective of the value of the PSTATE.I bit value.
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*/
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write_scr_el3(saved_scr_el3 | SCR_IRQ_BIT);
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/*
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* Enter standby state
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*
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* dsb & isb is good practice before using wfi to enter low power states
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*/
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dsb();
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isb();
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wfi();
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/*
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* Restore saved scr_el3 that has IRQ bit cleared as we don't want EL3
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* handling any further interrupts
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*/
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write_scr_el3(saved_scr_el3);
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}
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/*******************************************************************************
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* Handler called when an affinity instance is about to be turned on. The
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* level and mpidr determine the affinity instance.
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******************************************************************************/
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static int32_t tegra_pwr_domain_on(u_register_t mpidr)
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{
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return tegra_soc_pwr_domain_on(mpidr);
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}
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/*******************************************************************************
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* Handler called when a power domain is about to be turned off. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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static void tegra_pwr_domain_off(const psci_power_state_t *target_state)
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{
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(void)tegra_soc_pwr_domain_off(target_state);
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/* disable GICC */
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tegra_gic_cpuif_deactivate();
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}
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/*******************************************************************************
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* Handler called when a power domain is about to be suspended. The
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* target_state encodes the power state that each level should transition to.
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* This handler is called with SMP and data cache enabled, when
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* HW_ASSISTED_COHERENCY = 0
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******************************************************************************/
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void tegra_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
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{
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tegra_soc_pwr_domain_suspend_pwrdown_early(target_state);
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}
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/*******************************************************************************
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* Handler called when a power domain is about to be suspended. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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static void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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(void)tegra_soc_pwr_domain_suspend(target_state);
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/* disable GICC */
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tegra_gic_cpuif_deactivate();
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}
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/*******************************************************************************
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* Handler called at the end of the power domain suspend sequence. The
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* target_state encodes the power state that each level should transition to.
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******************************************************************************/
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static __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
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*target_state)
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{
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/* call the chip's power down handler */
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(void)tegra_soc_pwr_domain_power_down_wfi(target_state);
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/* Disable console if we are entering deep sleep. */
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if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
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PSTATE_ID_SOC_POWERDN) {
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INFO("%s: complete. Entering System Suspend...\n", __func__);
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console_flush();
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console_switch_state(0);
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}
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wfi();
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panic();
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}
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/*******************************************************************************
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* Handler called when a power domain has just been powered on after
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* being turned off earlier. The target_state encodes the low power state that
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* each level has woken up from.
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******************************************************************************/
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static void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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const plat_params_from_bl2_t *plat_params;
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/*
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* Check if we are exiting from deep sleep.
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*/
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if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
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PSTATE_ID_SOC_POWERDN) {
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/*
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* On entering System Suspend state, the GIC loses power
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* completely. Initialize the GIC global distributor and
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* GIC cpu interfaces.
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*/
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tegra_gic_init();
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/* Restart console output. */
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console_switch_state(CONSOLE_FLAG_RUNTIME);
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/*
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* Restore Memory Controller settings as it loses state
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* during system suspend.
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*/
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tegra_memctrl_restore_settings();
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/*
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* Security configuration to allow DRAM/device access.
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*/
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plat_params = bl31_get_plat_params();
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tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
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(uint32_t)plat_params->tzdram_size);
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} else {
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/*
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* Initialize the GIC cpu and distributor interfaces
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*/
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tegra_gic_pcpu_init();
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}
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/*
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* Reset hardware settings.
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*/
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(void)tegra_soc_pwr_domain_on_finish(target_state);
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}
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/*******************************************************************************
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* Handler called when a power domain has just been powered on after
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* having been suspended earlier. The target_state encodes the low power state
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* that each level has woken up from.
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******************************************************************************/
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static void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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tegra_pwr_domain_on_finish(target_state);
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}
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/*******************************************************************************
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* Handler called when the system wants to be powered off
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******************************************************************************/
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static __dead2 void tegra_system_off(void)
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{
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INFO("Powering down system...\n");
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tegra_soc_prepare_system_off();
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}
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/*******************************************************************************
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* Handler called when the system wants to be restarted.
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******************************************************************************/
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static __dead2 void tegra_system_reset(void)
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{
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INFO("Restarting system...\n");
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/* per-SoC system reset handler */
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(void)tegra_soc_prepare_system_reset();
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/* wait for the system to reset */
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for (;;) {
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;
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}
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}
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/*******************************************************************************
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* Handler called to check the validity of the power state parameter.
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******************************************************************************/
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static int32_t tegra_validate_power_state(uint32_t power_state,
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psci_power_state_t *req_state)
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{
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assert(req_state != NULL);
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return tegra_soc_validate_power_state(power_state, req_state);
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}
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/*******************************************************************************
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* Platform handler called to check the validity of the non secure entrypoint.
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******************************************************************************/
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static int32_t tegra_validate_ns_entrypoint(uintptr_t entrypoint)
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{
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int32_t ret = PSCI_E_INVALID_ADDRESS;
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/*
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* Check if the non secure entrypoint lies within the non
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* secure DRAM.
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*/
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if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) {
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ret = PSCI_E_SUCCESS;
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}
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return ret;
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}
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/*******************************************************************************
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* Export the platform handlers to enable psci to invoke them
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******************************************************************************/
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static plat_psci_ops_t tegra_plat_psci_ops = {
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.cpu_standby = tegra_cpu_standby,
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.pwr_domain_on = tegra_pwr_domain_on,
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.pwr_domain_off = tegra_pwr_domain_off,
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.pwr_domain_suspend_pwrdown_early = tegra_pwr_domain_suspend_pwrdown_early,
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.pwr_domain_suspend = tegra_pwr_domain_suspend,
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.pwr_domain_on_finish = tegra_pwr_domain_on_finish,
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.pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish,
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.pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi,
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.system_off = tegra_system_off,
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.system_reset = tegra_system_reset,
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.validate_power_state = tegra_validate_power_state,
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.validate_ns_entrypoint = tegra_validate_ns_entrypoint,
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.get_sys_suspend_power_state = tegra_get_sys_suspend_power_state,
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};
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/*******************************************************************************
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* Export the platform specific power ops and initialize Power Controller
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******************************************************************************/
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } };
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/*
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* Flush entrypoint variable to PoC since it will be
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* accessed after a reset with the caches turned off.
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*/
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tegra_sec_entry_point = sec_entrypoint;
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flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t));
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/*
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* Reset hardware settings.
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*/
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(void)tegra_soc_pwr_domain_on_finish(&target_state);
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/*
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* Disable System Suspend if the platform does not
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* support it
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*/
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if (!plat_supports_system_suspend()) {
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tegra_plat_psci_ops.get_sys_suspend_power_state = NULL;
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}
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/*
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* Initialize PSCI ops struct
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*/
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*psci_ops = &tegra_plat_psci_ops;
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return 0;
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}
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/*******************************************************************************
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* Platform handler to calculate the proper target power level at the
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* specified affinity level
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******************************************************************************/
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plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
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const plat_local_state_t *states,
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unsigned int ncpu)
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{
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return tegra_soc_get_target_pwr_state(lvl, states, ncpu);
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}
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