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235 lines
6.2 KiB
235 lines
6.2 KiB
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <string.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <common/fdt_fixup.h>
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#include <lib/optee_utils.h>
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#include <lib/utils.h>
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#include <plat/common/platform.h>
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#include "qemu_private.h"
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/* Data structure which holds the extents of the trusted SRAM for BL2 */
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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meminfo_t *mem_layout = (void *)arg1;
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/* Initialize the console to provide early debug support */
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qemu_console_init();
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/* Setup the BL2 memory layout */
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bl2_tzram_layout = *mem_layout;
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plat_qemu_io_setup();
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}
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static void security_setup(void)
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{
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/*
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* This is where a TrustZone address space controller and other
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* security related peripherals, would be configured.
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*/
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}
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static void update_dt(void)
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{
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int ret;
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void *fdt = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE;
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ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
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if (ret < 0) {
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ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret);
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return;
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}
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if (dt_add_psci_node(fdt)) {
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ERROR("Failed to add PSCI Device Tree node\n");
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return;
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}
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if (dt_add_psci_cpu_enable_methods(fdt)) {
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ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
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return;
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}
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ret = fdt_pack(fdt);
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if (ret < 0)
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ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret);
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}
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void bl2_platform_setup(void)
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{
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security_setup();
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update_dt();
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/* TODO Initialize timer */
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}
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#ifdef __aarch64__
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#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__)
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#else
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#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
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#endif
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void bl2_plat_arch_setup(void)
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{
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QEMU_CONFIGURE_BL2_MMU(bl2_tzram_layout.total_base,
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bl2_tzram_layout.total_size,
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BL_CODE_BASE, BL_CODE_END,
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BL_RO_DATA_BASE, BL_RO_DATA_END,
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BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
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}
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/*******************************************************************************
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* Gets SPSR for BL32 entry
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******************************************************************************/
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static uint32_t qemu_get_spsr_for_bl32_entry(void)
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{
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#ifdef __aarch64__
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL3-2 image.
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*/
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return 0;
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#else
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return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
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DISABLE_ALL_EXCEPTIONS);
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#endif
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}
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/*******************************************************************************
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* Gets SPSR for BL33 entry
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******************************************************************************/
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static uint32_t qemu_get_spsr_for_bl33_entry(void)
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{
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uint32_t spsr;
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#ifdef __aarch64__
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unsigned int mode;
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/* Figure out what mode we enter the non-secure world in */
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mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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#else
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spsr = SPSR_MODE32(MODE32_svc,
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plat_get_ns_image_entrypoint() & 0x1,
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SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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#endif
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return spsr;
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}
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static int qemu_bl2_handle_post_image_load(unsigned int image_id)
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{
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int err = 0;
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
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bl_mem_params_node_t *pager_mem_params = NULL;
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bl_mem_params_node_t *paged_mem_params = NULL;
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#endif
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assert(bl_mem_params);
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switch (image_id) {
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case BL32_IMAGE_ID:
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#if defined(SPD_opteed) || defined(AARCH32_SP_OPTEE)
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pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
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assert(pager_mem_params);
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paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
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assert(paged_mem_params);
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err = parse_optee_header(&bl_mem_params->ep_info,
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&pager_mem_params->image_info,
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&paged_mem_params->image_info);
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if (err != 0) {
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WARN("OPTEE header parse error.\n");
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}
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#if defined(SPD_opteed)
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/*
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* OP-TEE expect to receive DTB address in x2.
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* This will be copied into x2 by dispatcher.
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*/
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bl_mem_params->ep_info.args.arg3 = ARM_PRELOADED_DTB_BASE;
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#else /* case AARCH32_SP_OPTEE */
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bl_mem_params->ep_info.args.arg0 =
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bl_mem_params->ep_info.args.arg1;
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bl_mem_params->ep_info.args.arg1 = 0;
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bl_mem_params->ep_info.args.arg2 = ARM_PRELOADED_DTB_BASE;
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bl_mem_params->ep_info.args.arg3 = 0;
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#endif
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#endif
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bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl32_entry();
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break;
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case BL33_IMAGE_ID:
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#ifdef AARCH32_SP_OPTEE
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/* AArch32 only core: OP-TEE expects NSec EP in register LR */
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pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
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assert(pager_mem_params);
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pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
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#endif
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#if ARM_LINUX_KERNEL_AS_BL33
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/*
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* According to the file ``Documentation/arm64/booting.txt`` of
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* the Linux kernel tree, Linux expects the physical address of
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* the device tree blob (DTB) in x0, while x1-x3 are reserved
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* for future use and must be 0.
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*/
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bl_mem_params->ep_info.args.arg0 =
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(u_register_t)ARM_PRELOADED_DTB_BASE;
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bl_mem_params->ep_info.args.arg1 = 0U;
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bl_mem_params->ep_info.args.arg2 = 0U;
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bl_mem_params->ep_info.args.arg3 = 0U;
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#else
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/* BL33 expects to receive the primary CPU MPID (through r0) */
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bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
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#endif
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bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
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break;
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default:
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/* Do nothing in default case */
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break;
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}
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return err;
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}
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/*******************************************************************************
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* This function can be used by the platforms to update/use image
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* information for given `image_id`.
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******************************************************************************/
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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return qemu_bl2_handle_post_image_load(image_id);
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}
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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return NS_IMAGE_OFFSET;
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}
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