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285 lines
9.2 KiB
285 lines
9.2 KiB
/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Zhenyu Wang <zhenyuw@linux.intel.com>
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* Dominik Zeromski <dominik.zeromski@intel.com>
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*/
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#include <intel_bufmgr.h>
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#include <i915_drm.h>
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#include "intel_reg.h"
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#include "drmtest.h"
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#include "gpgpu_fill.h"
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#include "gpu_cmds.h"
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/* lib/i915/shaders/gpgpu/gpgpu_fill.gxa */
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static const uint32_t gen7_gpgpu_kernel[][4] = {
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{ 0x00400001, 0x20200231, 0x00000020, 0x00000000 },
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{ 0x00000041, 0x20400c21, 0x00000004, 0x00000010 },
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{ 0x00000001, 0x20440021, 0x00000018, 0x00000000 },
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{ 0x00600001, 0x20800021, 0x008d0000, 0x00000000 },
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{ 0x00200001, 0x20800021, 0x00450040, 0x00000000 },
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{ 0x00000001, 0x20880061, 0x00000000, 0x0000000f },
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{ 0x00800001, 0x20a00021, 0x00000020, 0x00000000 },
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{ 0x05800031, 0x24001ca8, 0x00000080, 0x060a8000 },
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{ 0x00600001, 0x2e000021, 0x008d0000, 0x00000000 },
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{ 0x07800031, 0x20001ca8, 0x00000e00, 0x82000010 },
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};
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static const uint32_t gen8_gpgpu_kernel[][4] = {
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{ 0x00400001, 0x20202288, 0x00000020, 0x00000000 },
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{ 0x00000041, 0x20400208, 0x06000004, 0x00000010 },
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{ 0x00000001, 0x20440208, 0x00000018, 0x00000000 },
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{ 0x00600001, 0x20800208, 0x008d0000, 0x00000000 },
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{ 0x00200001, 0x20800208, 0x00450040, 0x00000000 },
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{ 0x00000001, 0x20880608, 0x00000000, 0x0000000f },
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{ 0x00800001, 0x20a00208, 0x00000020, 0x00000000 },
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{ 0x0c800031, 0x24000a40, 0x0e000080, 0x060a8000 },
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{ 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
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{ 0x07800031, 0x20000a40, 0x0e000e00, 0x82000010 },
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};
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static const uint32_t gen9_gpgpu_kernel[][4] = {
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{ 0x00400001, 0x20202288, 0x00000020, 0x00000000 },
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{ 0x00000041, 0x20400208, 0x06000004, 0x00000010 },
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{ 0x00000001, 0x20440208, 0x00000018, 0x00000000 },
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{ 0x00600001, 0x20800208, 0x008d0000, 0x00000000 },
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{ 0x00200001, 0x20800208, 0x00450040, 0x00000000 },
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{ 0x00000001, 0x20880608, 0x00000000, 0x0000000f },
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{ 0x00800001, 0x20a00208, 0x00000020, 0x00000000 },
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{ 0x0c800031, 0x24000a40, 0x06000080, 0x060a8000 },
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{ 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
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{ 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 },
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};
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static const uint32_t gen11_gpgpu_kernel[][4] = {
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{ 0x00400001, 0x20202288, 0x00000020, 0x00000000 },
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{ 0x00000009, 0x20400208, 0x06000004, 0x00000004 },
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{ 0x00000001, 0x20440208, 0x00000018, 0x00000000 },
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{ 0x00600001, 0x20800208, 0x008d0000, 0x00000000 },
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{ 0x00200001, 0x20800208, 0x00450040, 0x00000000 },
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{ 0x00000001, 0x20880608, 0x00000000, 0x0000000f },
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{ 0x00800001, 0x20a00208, 0x00000020, 0x00000000 },
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{ 0x0c800031, 0x24000a40, 0x06000080, 0x040a8000 },
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{ 0x00600001, 0x2e000208, 0x008d0000, 0x00000000 },
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{ 0x07800031, 0x20000a40, 0x06000e00, 0x82000010 },
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};
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/*
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* This sets up the gpgpu pipeline,
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*
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* +---------------+ <---- 4096
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* | ^ |
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* | | |
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* | various |
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* | state |
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* | | |
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* |_______|_______| <---- 2048 + ?
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* | ^ |
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* | | |
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* | batch |
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* | commands |
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* | | |
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* | | |
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* +---------------+ <---- 0 + ?
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*
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*/
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#define BATCH_STATE_SPLIT 2048
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/* VFE STATE params */
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#define THREADS 1
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#define GEN7_GPGPU_URB_ENTRIES 0
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#define GEN8_GPGPU_URB_ENTRIES 1
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#define GPGPU_URB_SIZE 0
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#define GPGPU_CURBE_SIZE 1
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#define GEN7_VFE_STATE_GPGPU_MODE 1
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void
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gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
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const struct igt_buf *dst,
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unsigned int x, unsigned int y,
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unsigned int width, unsigned int height,
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uint8_t color)
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{
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uint32_t curbe_buffer, interface_descriptor;
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uint32_t batch_end;
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intel_batchbuffer_flush(batch);
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/* setup states */
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batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
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/*
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* const buffer needs to fill for every thread, but as we have just 1
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* thread per every group, so need only one curbe data.
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* For each thread, just use thread group ID for buffer offset.
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*/
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curbe_buffer = gen7_fill_curbe_buffer_data(batch, color);
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interface_descriptor = gen7_fill_interface_descriptor(batch, dst,
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gen7_gpgpu_kernel, sizeof(gen7_gpgpu_kernel));
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igt_assert(batch->ptr < &batch->buffer[4095]);
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batch->ptr = batch->buffer;
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/* GPGPU pipeline */
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OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU);
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gen7_emit_state_base_address(batch);
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gen7_emit_vfe_state(batch, THREADS, GEN7_GPGPU_URB_ENTRIES,
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GPGPU_URB_SIZE, GPGPU_CURBE_SIZE,
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GEN7_VFE_STATE_GPGPU_MODE);
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gen7_emit_curbe_load(batch, curbe_buffer);
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gen7_emit_interface_descriptor_load(batch, interface_descriptor);
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gen7_emit_gpgpu_walk(batch, x, y, width, height);
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OUT_BATCH(MI_BATCH_BUFFER_END);
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batch_end = intel_batchbuffer_align(batch, 8);
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igt_assert(batch_end < BATCH_STATE_SPLIT);
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gen7_render_flush(batch, batch_end);
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intel_batchbuffer_reset(batch);
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}
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void
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gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch,
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const struct igt_buf *dst,
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unsigned int x, unsigned int y,
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unsigned int width, unsigned int height,
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uint8_t color)
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{
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uint32_t curbe_buffer, interface_descriptor;
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uint32_t batch_end;
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intel_batchbuffer_flush(batch);
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/* setup states */
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batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
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/*
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* const buffer needs to fill for every thread, but as we have just 1
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* thread per every group, so need only one curbe data.
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* For each thread, just use thread group ID for buffer offset.
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*/
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curbe_buffer = gen7_fill_curbe_buffer_data(batch, color);
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interface_descriptor = gen8_fill_interface_descriptor(batch, dst,
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gen8_gpgpu_kernel, sizeof(gen8_gpgpu_kernel));
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igt_assert(batch->ptr < &batch->buffer[4095]);
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batch->ptr = batch->buffer;
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/* GPGPU pipeline */
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OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU);
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gen8_emit_state_base_address(batch);
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gen8_emit_vfe_state(batch, THREADS, GEN8_GPGPU_URB_ENTRIES,
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GPGPU_URB_SIZE, GPGPU_CURBE_SIZE);
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gen7_emit_curbe_load(batch, curbe_buffer);
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gen7_emit_interface_descriptor_load(batch, interface_descriptor);
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gen8_emit_gpgpu_walk(batch, x, y, width, height);
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OUT_BATCH(MI_BATCH_BUFFER_END);
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batch_end = intel_batchbuffer_align(batch, 8);
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igt_assert(batch_end < BATCH_STATE_SPLIT);
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gen7_render_flush(batch, batch_end);
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intel_batchbuffer_reset(batch);
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}
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static void
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__gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
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const struct igt_buf *dst,
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unsigned int x, unsigned int y,
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unsigned int width, unsigned int height,
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uint8_t color, const uint32_t kernel[][4],
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size_t kernel_size)
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{
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uint32_t curbe_buffer, interface_descriptor;
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uint32_t batch_end;
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intel_batchbuffer_flush(batch);
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/* setup states */
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batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
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/*
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* const buffer needs to fill for every thread, but as we have just 1
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* thread per every group, so need only one curbe data.
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* For each thread, just use thread group ID for buffer offset.
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*/
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curbe_buffer = gen7_fill_curbe_buffer_data(batch, color);
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interface_descriptor = gen8_fill_interface_descriptor(batch, dst,
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kernel, kernel_size);
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igt_assert(batch->ptr < &batch->buffer[4095]);
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batch->ptr = batch->buffer;
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/* GPGPU pipeline */
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OUT_BATCH(GEN7_PIPELINE_SELECT | GEN9_PIPELINE_SELECTION_MASK |
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PIPELINE_SELECT_GPGPU);
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gen9_emit_state_base_address(batch);
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gen8_emit_vfe_state(batch, THREADS, GEN8_GPGPU_URB_ENTRIES,
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GPGPU_URB_SIZE, GPGPU_CURBE_SIZE);
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gen7_emit_curbe_load(batch, curbe_buffer);
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gen7_emit_interface_descriptor_load(batch, interface_descriptor);
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gen8_emit_gpgpu_walk(batch, x, y, width, height);
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OUT_BATCH(MI_BATCH_BUFFER_END);
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batch_end = intel_batchbuffer_align(batch, 8);
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igt_assert(batch_end < BATCH_STATE_SPLIT);
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gen7_render_flush(batch, batch_end);
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intel_batchbuffer_reset(batch);
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}
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void gen9_gpgpu_fillfunc(struct intel_batchbuffer *batch,
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const struct igt_buf *dst,
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unsigned int x, unsigned int y,
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unsigned int width, unsigned int height,
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uint8_t color)
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{
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__gen9_gpgpu_fillfunc(batch, dst, x, y, width, height, color,
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gen9_gpgpu_kernel, sizeof(gen9_gpgpu_kernel));
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}
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void gen11_gpgpu_fillfunc(struct intel_batchbuffer *batch,
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const struct igt_buf *dst,
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unsigned int x, unsigned int y,
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unsigned int width, unsigned int height,
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uint8_t color)
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{
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__gen9_gpgpu_fillfunc(batch, dst, x, y, width, height, color,
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gen11_gpgpu_kernel, sizeof(gen11_gpgpu_kernel));
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}
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