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917 lines
28 KiB
917 lines
28 KiB
//===--- X86.h - Declare X86 target feature support -------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares X86 TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_X86_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_X86_H
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#include "OSTargets.h"
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/X86TargetParser.h"
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namespace clang {
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namespace targets {
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static const unsigned X86AddrSpaceMap[] = {
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0, // Default
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0, // opencl_global
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0, // opencl_local
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0, // opencl_constant
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0, // opencl_private
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0, // opencl_generic
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0, // opencl_global_device
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0, // opencl_global_host
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0, // cuda_device
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0, // cuda_constant
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0, // cuda_shared
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270, // ptr32_sptr
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271, // ptr32_uptr
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272 // ptr64
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};
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// X86 target abstract base class; x86-32 and x86-64 are very close, so
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// most of the implementation can be shared.
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class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
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enum X86SSEEnum {
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NoSSE,
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SSE1,
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SSE2,
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SSE3,
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SSSE3,
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SSE41,
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SSE42,
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AVX,
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AVX2,
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AVX512F
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} SSELevel = NoSSE;
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enum MMX3DNowEnum {
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NoMMX3DNow,
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MMX,
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AMD3DNow,
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AMD3DNowAthlon
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} MMX3DNowLevel = NoMMX3DNow;
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enum XOPEnum { NoXOP, SSE4A, FMA4, XOP } XOPLevel = NoXOP;
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enum AddrSpace { ptr32_sptr = 270, ptr32_uptr = 271, ptr64 = 272 };
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bool HasAES = false;
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bool HasVAES = false;
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bool HasPCLMUL = false;
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bool HasVPCLMULQDQ = false;
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bool HasGFNI = false;
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bool HasLZCNT = false;
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bool HasRDRND = false;
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bool HasFSGSBASE = false;
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bool HasBMI = false;
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bool HasBMI2 = false;
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bool HasPOPCNT = false;
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bool HasRTM = false;
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bool HasPRFCHW = false;
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bool HasRDSEED = false;
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bool HasADX = false;
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bool HasTBM = false;
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bool HasLWP = false;
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bool HasFMA = false;
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bool HasF16C = false;
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bool HasAVX512CD = false;
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bool HasAVX512VPOPCNTDQ = false;
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bool HasAVX512VNNI = false;
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bool HasAVX512BF16 = false;
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bool HasAVX512ER = false;
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bool HasAVX512PF = false;
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bool HasAVX512DQ = false;
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bool HasAVX512BITALG = false;
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bool HasAVX512BW = false;
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bool HasAVX512VL = false;
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bool HasAVX512VBMI = false;
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bool HasAVX512VBMI2 = false;
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bool HasAVX512IFMA = false;
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bool HasAVX512VP2INTERSECT = false;
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bool HasSHA = false;
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bool HasSHSTK = false;
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bool HasSGX = false;
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bool HasCX8 = false;
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bool HasCX16 = false;
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bool HasFXSR = false;
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bool HasXSAVE = false;
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bool HasXSAVEOPT = false;
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bool HasXSAVEC = false;
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bool HasXSAVES = false;
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bool HasMWAITX = false;
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bool HasCLZERO = false;
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bool HasCLDEMOTE = false;
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bool HasPCONFIG = false;
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bool HasPKU = false;
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bool HasCLFLUSHOPT = false;
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bool HasCLWB = false;
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bool HasMOVBE = false;
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bool HasPREFETCHWT1 = false;
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bool HasRDPID = false;
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bool HasRetpolineExternalThunk = false;
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bool HasLAHFSAHF = false;
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bool HasWBNOINVD = false;
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bool HasWAITPKG = false;
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bool HasMOVDIRI = false;
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bool HasMOVDIR64B = false;
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bool HasPTWRITE = false;
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bool HasINVPCID = false;
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bool HasENQCMD = false;
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bool HasKL = false; // For key locker
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bool HasWIDEKL = false; // For wide key locker
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bool HasHRESET = false;
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bool HasAVXVNNI = false;
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bool HasAMXTILE = false;
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bool HasAMXINT8 = false;
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bool HasAMXBF16 = false;
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bool HasSERIALIZE = false;
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bool HasTSXLDTRK = false;
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bool HasUINTR = false;
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protected:
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llvm::X86::CPUKind CPU = llvm::X86::CK_None;
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enum FPMathKind { FP_Default, FP_SSE, FP_387 } FPMath = FP_Default;
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public:
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X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &)
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: TargetInfo(Triple) {
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LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
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AddrSpaceMap = &X86AddrSpaceMap;
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HasStrictFP = true;
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bool IsWinCOFF =
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getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
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if (IsWinCOFF)
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MaxVectorAlign = MaxTLSAlign = 8192u * getCharWidth();
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}
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const char *getLongDoubleMangling() const override {
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return LongDoubleFormat == &llvm::APFloat::IEEEquad() ? "g" : "e";
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}
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unsigned getFloatEvalMethod() const override {
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// X87 evaluates with 80 bits "long double" precision.
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return SSELevel == NoSSE ? 2 : 0;
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}
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ArrayRef<const char *> getGCCRegNames() const override;
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ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
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return None;
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}
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ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override;
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bool isSPRegName(StringRef RegName) const override {
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return RegName.equals("esp") || RegName.equals("rsp");
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}
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bool validateCpuSupports(StringRef Name) const override;
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bool validateCpuIs(StringRef Name) const override;
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bool validateCPUSpecificCPUDispatch(StringRef Name) const override;
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char CPUSpecificManglingCharacter(StringRef Name) const override;
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void getCPUSpecificCPUDispatchFeatures(
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StringRef Name,
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llvm::SmallVectorImpl<StringRef> &Features) const override;
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Optional<unsigned> getCPUCacheLineSize() const override;
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bool validateAsmConstraint(const char *&Name,
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TargetInfo::ConstraintInfo &info) const override;
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bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
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bool &HasSizeMismatch) const override {
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// esp and ebp are the only 32-bit registers the x86 backend can currently
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// handle.
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if (RegName.equals("esp") || RegName.equals("ebp")) {
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// Check that the register size is 32-bit.
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HasSizeMismatch = RegSize != 32;
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return true;
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}
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return false;
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}
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bool validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
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StringRef Constraint, unsigned Size) const override;
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bool validateInputSize(const llvm::StringMap<bool> &FeatureMap,
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StringRef Constraint, unsigned Size) const override;
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virtual bool
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checkCFProtectionReturnSupported(DiagnosticsEngine &Diags) const override {
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return true;
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};
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virtual bool
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checkCFProtectionBranchSupported(DiagnosticsEngine &Diags) const override {
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return true;
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};
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virtual bool validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
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StringRef Constraint, unsigned Size) const;
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std::string convertConstraint(const char *&Constraint) const override;
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const char *getClobbers() const override {
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return "~{dirflag},~{fpsr},~{flags}";
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}
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StringRef getConstraintRegister(StringRef Constraint,
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StringRef Expression) const override {
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StringRef::iterator I, E;
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for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) {
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if (isalpha(*I) || *I == '@')
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break;
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}
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if (I == E)
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return "";
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switch (*I) {
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// For the register constraints, return the matching register name
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case 'a':
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return "ax";
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case 'b':
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return "bx";
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case 'c':
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return "cx";
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case 'd':
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return "dx";
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case 'S':
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return "si";
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case 'D':
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return "di";
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// In case the constraint is 'r' we need to return Expression
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case 'r':
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return Expression;
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// Double letters Y<x> constraints
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case 'Y':
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if ((++I != E) && ((*I == '0') || (*I == 'z')))
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return "xmm0";
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break;
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default:
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break;
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}
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return "";
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}
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bool useFP16ConversionIntrinsics() const override {
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return false;
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}
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override;
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void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
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bool Enabled) const final;
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bool
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initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
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StringRef CPU,
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const std::vector<std::string> &FeaturesVec) const override;
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bool isValidFeatureName(StringRef Name) const override;
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bool hasFeature(StringRef Feature) const final;
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bool handleTargetFeatures(std::vector<std::string> &Features,
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DiagnosticsEngine &Diags) override;
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StringRef getABI() const override {
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if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
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return "avx512";
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if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
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return "avx";
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if (getTriple().getArch() == llvm::Triple::x86 &&
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MMX3DNowLevel == NoMMX3DNow)
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return "no-mmx";
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return "";
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}
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bool supportsTargetAttributeTune() const override {
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return true;
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}
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bool isValidCPUName(StringRef Name) const override {
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bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
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return llvm::X86::parseArchX86(Name, Only64Bit) != llvm::X86::CK_None;
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}
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bool isValidTuneCPUName(StringRef Name) const override {
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if (Name == "generic")
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return true;
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// Allow 32-bit only CPUs regardless of 64-bit mode unlike isValidCPUName.
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// NOTE: gcc rejects 32-bit mtune CPUs in 64-bit mode. But being lenient
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// since mtune was ignored by clang for so long.
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return llvm::X86::parseTuneCPU(Name) != llvm::X86::CK_None;
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}
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void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
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void fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const override;
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bool setCPU(const std::string &Name) override {
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bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
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CPU = llvm::X86::parseArchX86(Name, Only64Bit);
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return CPU != llvm::X86::CK_None;
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}
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unsigned multiVersionSortPriority(StringRef Name) const override;
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bool setFPMath(StringRef Name) override;
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CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
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// Most of the non-ARM calling conventions are i386 conventions.
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switch (CC) {
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case CC_X86ThisCall:
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case CC_X86FastCall:
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case CC_X86StdCall:
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case CC_X86VectorCall:
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case CC_X86RegCall:
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case CC_C:
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case CC_PreserveMost:
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case CC_Swift:
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case CC_X86Pascal:
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case CC_IntelOclBicc:
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case CC_OpenCLKernel:
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return CCCR_OK;
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default:
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return CCCR_Warning;
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}
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}
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CallingConv getDefaultCallingConv() const override {
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return CC_C;
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}
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bool hasSjLjLowering() const override { return true; }
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void setSupportedOpenCLOpts() override {
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getSupportedOpenCLOpts().supportAll();
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}
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uint64_t getPointerWidthV(unsigned AddrSpace) const override {
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if (AddrSpace == ptr32_sptr || AddrSpace == ptr32_uptr)
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return 32;
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if (AddrSpace == ptr64)
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return 64;
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return PointerWidth;
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}
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uint64_t getPointerAlignV(unsigned AddrSpace) const override {
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return getPointerWidthV(AddrSpace);
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}
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};
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// X86-32 generic target
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class LLVM_LIBRARY_VISIBILITY X86_32TargetInfo : public X86TargetInfo {
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public:
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X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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: X86TargetInfo(Triple, Opts) {
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DoubleAlign = LongLongAlign = 32;
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LongDoubleWidth = 96;
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LongDoubleAlign = 32;
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SuitableAlign = 128;
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resetDataLayout(Triple.isOSBinFormatMachO() ?
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"e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-"
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"f80:32-n8:16:32-S128" :
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"e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-"
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"f80:32-n8:16:32-S128");
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SizeType = UnsignedInt;
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PtrDiffType = SignedInt;
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IntPtrType = SignedInt;
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RegParmMax = 3;
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// Use fpret for all types.
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RealTypeUsesObjCFPRet =
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((1 << TargetInfo::Float) | (1 << TargetInfo::Double) |
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(1 << TargetInfo::LongDouble));
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// x86-32 has atomics up to 8 bytes
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MaxAtomicPromoteWidth = 64;
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MaxAtomicInlineWidth = 32;
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}
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BuiltinVaListKind getBuiltinVaListKind() const override {
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return TargetInfo::CharPtrBuiltinVaList;
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}
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int getEHDataRegisterNumber(unsigned RegNo) const override {
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if (RegNo == 0)
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return 0;
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if (RegNo == 1)
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return 2;
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return -1;
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}
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bool validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
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StringRef Constraint, unsigned Size) const override {
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switch (Constraint[0]) {
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default:
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break;
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case 'R':
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case 'q':
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case 'Q':
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case 'a':
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case 'b':
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case 'c':
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case 'd':
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case 'S':
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case 'D':
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return Size <= 32;
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case 'A':
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return Size <= 64;
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}
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return X86TargetInfo::validateOperandSize(FeatureMap, Constraint, Size);
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}
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void setMaxAtomicWidth() override {
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if (hasFeature("cx8"))
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MaxAtomicInlineWidth = 64;
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}
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ArrayRef<Builtin::Info> getTargetBuiltins() const override;
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bool hasExtIntType() const override { return true; }
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};
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class LLVM_LIBRARY_VISIBILITY NetBSDI386TargetInfo
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: public NetBSDTargetInfo<X86_32TargetInfo> {
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public:
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NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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: NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
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unsigned getFloatEvalMethod() const override {
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unsigned Major, Minor, Micro;
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getTriple().getOSVersion(Major, Minor, Micro);
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// New NetBSD uses the default rounding mode.
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if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
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return X86_32TargetInfo::getFloatEvalMethod();
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// NetBSD before 6.99.26 defaults to "double" rounding.
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return 1;
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}
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};
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class LLVM_LIBRARY_VISIBILITY OpenBSDI386TargetInfo
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: public OpenBSDTargetInfo<X86_32TargetInfo> {
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public:
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OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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: OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {
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SizeType = UnsignedLong;
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IntPtrType = SignedLong;
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PtrDiffType = SignedLong;
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}
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};
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class LLVM_LIBRARY_VISIBILITY DarwinI386TargetInfo
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: public DarwinTargetInfo<X86_32TargetInfo> {
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public:
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DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
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: DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) {
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LongDoubleWidth = 128;
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LongDoubleAlign = 128;
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SuitableAlign = 128;
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MaxVectorAlign = 256;
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// The watchOS simulator uses the builtin bool type for Objective-C.
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llvm::Triple T = llvm::Triple(Triple);
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if (T.isWatchOS())
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UseSignedCharForObjCBool = false;
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SizeType = UnsignedLong;
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IntPtrType = SignedLong;
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resetDataLayout("e-m:o-p:32:32-p270:32:32-p271:32:32-p272:64:64-f64:32:64-"
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"f80:128-n8:16:32-S128");
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HasAlignMac68kSupport = true;
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}
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bool handleTargetFeatures(std::vector<std::string> &Features,
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DiagnosticsEngine &Diags) override {
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if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
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Diags))
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return false;
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// We now know the features we have: we can decide how to align vectors.
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MaxVectorAlign =
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hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
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return true;
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}
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};
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// x86-32 Windows target
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class LLVM_LIBRARY_VISIBILITY WindowsX86_32TargetInfo
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: public WindowsTargetInfo<X86_32TargetInfo> {
|
|
public:
|
|
WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) {
|
|
DoubleAlign = LongLongAlign = 64;
|
|
bool IsWinCOFF =
|
|
getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
|
|
resetDataLayout(IsWinCOFF ? "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:"
|
|
"64-i64:64-f80:32-n8:16:32-a:0:32-S32"
|
|
: "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:"
|
|
"64-i64:64-f80:32-n8:16:32-a:0:32-S32");
|
|
}
|
|
};
|
|
|
|
// x86-32 Windows Visual Studio target
|
|
class LLVM_LIBRARY_VISIBILITY MicrosoftX86_32TargetInfo
|
|
: public WindowsX86_32TargetInfo {
|
|
public:
|
|
MicrosoftX86_32TargetInfo(const llvm::Triple &Triple,
|
|
const TargetOptions &Opts)
|
|
: WindowsX86_32TargetInfo(Triple, Opts) {
|
|
LongDoubleWidth = LongDoubleAlign = 64;
|
|
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
|
|
}
|
|
|
|
void getTargetDefines(const LangOptions &Opts,
|
|
MacroBuilder &Builder) const override {
|
|
WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
|
|
// The value of the following reflects processor type.
|
|
// 300=386, 400=486, 500=Pentium, 600=Blend (default)
|
|
// We lost the original triple, so we use the default.
|
|
Builder.defineMacro("_M_IX86", "600");
|
|
}
|
|
};
|
|
|
|
// x86-32 MinGW target
|
|
class LLVM_LIBRARY_VISIBILITY MinGWX86_32TargetInfo
|
|
: public WindowsX86_32TargetInfo {
|
|
public:
|
|
MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: WindowsX86_32TargetInfo(Triple, Opts) {
|
|
HasFloat128 = true;
|
|
}
|
|
|
|
void getTargetDefines(const LangOptions &Opts,
|
|
MacroBuilder &Builder) const override {
|
|
WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
|
|
Builder.defineMacro("_X86_");
|
|
}
|
|
};
|
|
|
|
// x86-32 Cygwin target
|
|
class LLVM_LIBRARY_VISIBILITY CygwinX86_32TargetInfo : public X86_32TargetInfo {
|
|
public:
|
|
CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: X86_32TargetInfo(Triple, Opts) {
|
|
this->WCharType = TargetInfo::UnsignedShort;
|
|
DoubleAlign = LongLongAlign = 64;
|
|
resetDataLayout("e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:"
|
|
"32-n8:16:32-a:0:32-S32");
|
|
}
|
|
|
|
void getTargetDefines(const LangOptions &Opts,
|
|
MacroBuilder &Builder) const override {
|
|
X86_32TargetInfo::getTargetDefines(Opts, Builder);
|
|
Builder.defineMacro("_X86_");
|
|
Builder.defineMacro("__CYGWIN__");
|
|
Builder.defineMacro("__CYGWIN32__");
|
|
addCygMingDefines(Opts, Builder);
|
|
DefineStd(Builder, "unix", Opts);
|
|
if (Opts.CPlusPlus)
|
|
Builder.defineMacro("_GNU_SOURCE");
|
|
}
|
|
};
|
|
|
|
// x86-32 Haiku target
|
|
class LLVM_LIBRARY_VISIBILITY HaikuX86_32TargetInfo
|
|
: public HaikuTargetInfo<X86_32TargetInfo> {
|
|
public:
|
|
HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) {}
|
|
|
|
void getTargetDefines(const LangOptions &Opts,
|
|
MacroBuilder &Builder) const override {
|
|
HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
|
|
Builder.defineMacro("__INTEL__");
|
|
}
|
|
};
|
|
|
|
// X86-32 MCU target
|
|
class LLVM_LIBRARY_VISIBILITY MCUX86_32TargetInfo : public X86_32TargetInfo {
|
|
public:
|
|
MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: X86_32TargetInfo(Triple, Opts) {
|
|
LongDoubleWidth = 64;
|
|
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
|
|
resetDataLayout("e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:32-f64:"
|
|
"32-f128:32-n8:16:32-a:0:32-S32");
|
|
WIntType = UnsignedInt;
|
|
}
|
|
|
|
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
|
|
// On MCU we support only C calling convention.
|
|
return CC == CC_C ? CCCR_OK : CCCR_Warning;
|
|
}
|
|
|
|
void getTargetDefines(const LangOptions &Opts,
|
|
MacroBuilder &Builder) const override {
|
|
X86_32TargetInfo::getTargetDefines(Opts, Builder);
|
|
Builder.defineMacro("__iamcu");
|
|
Builder.defineMacro("__iamcu__");
|
|
}
|
|
|
|
bool allowsLargerPreferedTypeAlignment() const override { return false; }
|
|
};
|
|
|
|
// x86-32 RTEMS target
|
|
class LLVM_LIBRARY_VISIBILITY RTEMSX86_32TargetInfo : public X86_32TargetInfo {
|
|
public:
|
|
RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: X86_32TargetInfo(Triple, Opts) {
|
|
SizeType = UnsignedLong;
|
|
IntPtrType = SignedLong;
|
|
PtrDiffType = SignedLong;
|
|
}
|
|
|
|
void getTargetDefines(const LangOptions &Opts,
|
|
MacroBuilder &Builder) const override {
|
|
X86_32TargetInfo::getTargetDefines(Opts, Builder);
|
|
Builder.defineMacro("__INTEL__");
|
|
Builder.defineMacro("__rtems__");
|
|
}
|
|
};
|
|
|
|
// x86-64 generic target
|
|
class LLVM_LIBRARY_VISIBILITY X86_64TargetInfo : public X86TargetInfo {
|
|
public:
|
|
X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: X86TargetInfo(Triple, Opts) {
|
|
const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
|
|
bool IsWinCOFF =
|
|
getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
|
|
LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
|
|
LongDoubleWidth = 128;
|
|
LongDoubleAlign = 128;
|
|
LargeArrayMinWidth = 128;
|
|
LargeArrayAlign = 128;
|
|
SuitableAlign = 128;
|
|
SizeType = IsX32 ? UnsignedInt : UnsignedLong;
|
|
PtrDiffType = IsX32 ? SignedInt : SignedLong;
|
|
IntPtrType = IsX32 ? SignedInt : SignedLong;
|
|
IntMaxType = IsX32 ? SignedLongLong : SignedLong;
|
|
Int64Type = IsX32 ? SignedLongLong : SignedLong;
|
|
RegParmMax = 6;
|
|
|
|
// Pointers are 32-bit in x32.
|
|
resetDataLayout(IsX32 ? "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-"
|
|
"i64:64-f80:128-n8:16:32:64-S128"
|
|
: IsWinCOFF ? "e-m:w-p270:32:32-p271:32:32-p272:64:"
|
|
"64-i64:64-f80:128-n8:16:32:64-S128"
|
|
: "e-m:e-p270:32:32-p271:32:32-p272:64:"
|
|
"64-i64:64-f80:128-n8:16:32:64-S128");
|
|
|
|
// Use fpret only for long double.
|
|
RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
|
|
|
|
// Use fp2ret for _Complex long double.
|
|
ComplexLongDoubleUsesFP2Ret = true;
|
|
|
|
// Make __builtin_ms_va_list available.
|
|
HasBuiltinMSVaList = true;
|
|
|
|
// x86-64 has atomics up to 16 bytes.
|
|
MaxAtomicPromoteWidth = 128;
|
|
MaxAtomicInlineWidth = 64;
|
|
}
|
|
|
|
BuiltinVaListKind getBuiltinVaListKind() const override {
|
|
return TargetInfo::X86_64ABIBuiltinVaList;
|
|
}
|
|
|
|
int getEHDataRegisterNumber(unsigned RegNo) const override {
|
|
if (RegNo == 0)
|
|
return 0;
|
|
if (RegNo == 1)
|
|
return 1;
|
|
return -1;
|
|
}
|
|
|
|
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
|
|
switch (CC) {
|
|
case CC_C:
|
|
case CC_Swift:
|
|
case CC_X86VectorCall:
|
|
case CC_IntelOclBicc:
|
|
case CC_Win64:
|
|
case CC_PreserveMost:
|
|
case CC_PreserveAll:
|
|
case CC_X86RegCall:
|
|
case CC_OpenCLKernel:
|
|
return CCCR_OK;
|
|
default:
|
|
return CCCR_Warning;
|
|
}
|
|
}
|
|
|
|
CallingConv getDefaultCallingConv() const override {
|
|
return CC_C;
|
|
}
|
|
|
|
// for x32 we need it here explicitly
|
|
bool hasInt128Type() const override { return true; }
|
|
|
|
unsigned getUnwindWordWidth() const override { return 64; }
|
|
|
|
unsigned getRegisterWidth() const override { return 64; }
|
|
|
|
bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
|
|
bool &HasSizeMismatch) const override {
|
|
// rsp and rbp are the only 64-bit registers the x86 backend can currently
|
|
// handle.
|
|
if (RegName.equals("rsp") || RegName.equals("rbp")) {
|
|
// Check that the register size is 64-bit.
|
|
HasSizeMismatch = RegSize != 64;
|
|
return true;
|
|
}
|
|
|
|
// Check if the register is a 32-bit register the backend can handle.
|
|
return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
|
|
HasSizeMismatch);
|
|
}
|
|
|
|
void setMaxAtomicWidth() override {
|
|
if (hasFeature("cx16"))
|
|
MaxAtomicInlineWidth = 128;
|
|
}
|
|
|
|
ArrayRef<Builtin::Info> getTargetBuiltins() const override;
|
|
|
|
bool hasExtIntType() const override { return true; }
|
|
};
|
|
|
|
// x86-64 Windows target
|
|
class LLVM_LIBRARY_VISIBILITY WindowsX86_64TargetInfo
|
|
: public WindowsTargetInfo<X86_64TargetInfo> {
|
|
public:
|
|
WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) {
|
|
LongWidth = LongAlign = 32;
|
|
DoubleAlign = LongLongAlign = 64;
|
|
IntMaxType = SignedLongLong;
|
|
Int64Type = SignedLongLong;
|
|
SizeType = UnsignedLongLong;
|
|
PtrDiffType = SignedLongLong;
|
|
IntPtrType = SignedLongLong;
|
|
}
|
|
|
|
BuiltinVaListKind getBuiltinVaListKind() const override {
|
|
return TargetInfo::CharPtrBuiltinVaList;
|
|
}
|
|
|
|
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
|
|
switch (CC) {
|
|
case CC_X86StdCall:
|
|
case CC_X86ThisCall:
|
|
case CC_X86FastCall:
|
|
return CCCR_Ignore;
|
|
case CC_C:
|
|
case CC_X86VectorCall:
|
|
case CC_IntelOclBicc:
|
|
case CC_PreserveMost:
|
|
case CC_PreserveAll:
|
|
case CC_X86_64SysV:
|
|
case CC_Swift:
|
|
case CC_X86RegCall:
|
|
case CC_OpenCLKernel:
|
|
return CCCR_OK;
|
|
default:
|
|
return CCCR_Warning;
|
|
}
|
|
}
|
|
};
|
|
|
|
// x86-64 Windows Visual Studio target
|
|
class LLVM_LIBRARY_VISIBILITY MicrosoftX86_64TargetInfo
|
|
: public WindowsX86_64TargetInfo {
|
|
public:
|
|
MicrosoftX86_64TargetInfo(const llvm::Triple &Triple,
|
|
const TargetOptions &Opts)
|
|
: WindowsX86_64TargetInfo(Triple, Opts) {
|
|
LongDoubleWidth = LongDoubleAlign = 64;
|
|
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
|
|
}
|
|
|
|
void getTargetDefines(const LangOptions &Opts,
|
|
MacroBuilder &Builder) const override {
|
|
WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
|
|
Builder.defineMacro("_M_X64", "100");
|
|
Builder.defineMacro("_M_AMD64", "100");
|
|
}
|
|
|
|
TargetInfo::CallingConvKind
|
|
getCallingConvKind(bool ClangABICompat4) const override {
|
|
return CCK_MicrosoftWin64;
|
|
}
|
|
};
|
|
|
|
// x86-64 MinGW target
|
|
class LLVM_LIBRARY_VISIBILITY MinGWX86_64TargetInfo
|
|
: public WindowsX86_64TargetInfo {
|
|
public:
|
|
MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: WindowsX86_64TargetInfo(Triple, Opts) {
|
|
// Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
|
|
// with x86 FP ops. Weird.
|
|
LongDoubleWidth = LongDoubleAlign = 128;
|
|
LongDoubleFormat = &llvm::APFloat::x87DoubleExtended();
|
|
HasFloat128 = true;
|
|
}
|
|
};
|
|
|
|
// x86-64 Cygwin target
|
|
class LLVM_LIBRARY_VISIBILITY CygwinX86_64TargetInfo : public X86_64TargetInfo {
|
|
public:
|
|
CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: X86_64TargetInfo(Triple, Opts) {
|
|
this->WCharType = TargetInfo::UnsignedShort;
|
|
TLSSupported = false;
|
|
}
|
|
|
|
void getTargetDefines(const LangOptions &Opts,
|
|
MacroBuilder &Builder) const override {
|
|
X86_64TargetInfo::getTargetDefines(Opts, Builder);
|
|
Builder.defineMacro("__x86_64__");
|
|
Builder.defineMacro("__CYGWIN__");
|
|
Builder.defineMacro("__CYGWIN64__");
|
|
addCygMingDefines(Opts, Builder);
|
|
DefineStd(Builder, "unix", Opts);
|
|
if (Opts.CPlusPlus)
|
|
Builder.defineMacro("_GNU_SOURCE");
|
|
}
|
|
};
|
|
|
|
class LLVM_LIBRARY_VISIBILITY DarwinX86_64TargetInfo
|
|
: public DarwinTargetInfo<X86_64TargetInfo> {
|
|
public:
|
|
DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) {
|
|
Int64Type = SignedLongLong;
|
|
// The 64-bit iOS simulator uses the builtin bool type for Objective-C.
|
|
llvm::Triple T = llvm::Triple(Triple);
|
|
if (T.isiOS())
|
|
UseSignedCharForObjCBool = false;
|
|
resetDataLayout("e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:"
|
|
"16:32:64-S128");
|
|
}
|
|
|
|
bool handleTargetFeatures(std::vector<std::string> &Features,
|
|
DiagnosticsEngine &Diags) override {
|
|
if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
|
|
Diags))
|
|
return false;
|
|
// We now know the features we have: we can decide how to align vectors.
|
|
MaxVectorAlign =
|
|
hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
|
|
return true;
|
|
}
|
|
};
|
|
|
|
class LLVM_LIBRARY_VISIBILITY OpenBSDX86_64TargetInfo
|
|
: public OpenBSDTargetInfo<X86_64TargetInfo> {
|
|
public:
|
|
OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) {
|
|
IntMaxType = SignedLongLong;
|
|
Int64Type = SignedLongLong;
|
|
}
|
|
};
|
|
|
|
// x86_32 Android target
|
|
class LLVM_LIBRARY_VISIBILITY AndroidX86_32TargetInfo
|
|
: public LinuxTargetInfo<X86_32TargetInfo> {
|
|
public:
|
|
AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) {
|
|
SuitableAlign = 32;
|
|
LongDoubleWidth = 64;
|
|
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
|
|
}
|
|
};
|
|
|
|
// x86_64 Android target
|
|
class LLVM_LIBRARY_VISIBILITY AndroidX86_64TargetInfo
|
|
: public LinuxTargetInfo<X86_64TargetInfo> {
|
|
public:
|
|
AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
|
|
: LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) {
|
|
LongDoubleFormat = &llvm::APFloat::IEEEquad();
|
|
}
|
|
};
|
|
} // namespace targets
|
|
} // namespace clang
|
|
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_X86_H
|