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66 lines
2.7 KiB
66 lines
2.7 KiB
..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid8_imask:
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imask
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===========================
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This operand is a mask which controls indexing mode for operands of subsequent instructions.
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Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*.
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Value 1 enables indexing and value 0 disables it.
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===== ========================================
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Bit Meaning
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===== ========================================
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0 Enables or disables *src0* indexing.
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1 Enables or disables *src1* indexing.
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2 Enables or disables *src2* indexing.
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3 Enables or disables *dst* indexing.
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===== ========================================
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..15.
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* A *gpr_idx* value described below.
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==================================== ===========================================
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Gpr_idx Value Syntax Description
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==================================== ===========================================
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gpr_idx(*<operands>*) Enable indexing for specified *operands*
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and disable it for the rest.
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*Operands* is a comma-separated list of
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values which may include:
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* "SRC0" - enable *src0* indexing.
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* "SRC1" - enable *src1* indexing.
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* "SRC2" - enable *src2* indexing.
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* "DST" - enable *dst* indexing.
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Each of these values may be specified only
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once.
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*Operands* list may be empty; this syntax
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disables indexing for all operands.
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==================================== ===========================================
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Examples:
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.. parsed-literal::
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s_set_gpr_idx_mode 0
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s_set_gpr_idx_mode gpr_idx() // the same as above
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s_set_gpr_idx_mode 15
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s_set_gpr_idx_mode gpr_idx(DST,SRC0,SRC1,SRC2) // the same as above
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s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) // the same as above
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s_set_gpr_idx_mode gpr_idx(DST,SRC1)
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