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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X64
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define i16 @test_shl_i4(i16 %v, i16 %a, i16 %b) {
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; Let's say the arguments are the following unsigned
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; integers in two’s complement representation:
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;
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; %v: 77 (0000 0000 0100 1101)
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; %a: 74 (0000 0000 0100 1010)
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; %b: 72 (0000 0000 0100 1000)
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; X64-LABEL: test_shl_i4:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $esi killed $esi def $rsi
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; X64-NEXT: # kill: def $edx killed $edx def $rdx
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; X64-NEXT: leal (%rdx,%rsi), %ecx
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; X64-NEXT: andb $15, %cl
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; X64-NEXT: # kill: def $cl killed $cl killed $ecx
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; X64-NEXT: shlb %cl, %dil
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; X64-NEXT: movzbl %dil, %eax
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; X64-NEXT: andw $15, %ax
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: retq
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%v.t = trunc i16 %v to i4 ; %v.t: 13 (1101)
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%a.t = trunc i16 %a to i4 ; %a.t: 10 (1010)
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%b.t = trunc i16 %b to i4 ; %b.t: 8 (1000)
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%n.t = add i4 %a.t, %b.t ; %n.t: 2 (0010)
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%r.t = shl i4 %v.t, %n.t ; %r.t: 4 (0100)
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%r = zext i4 %r.t to i16
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; %r: 4 (0000 0000 0000 0100)
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ret i16 %r
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; %di: 77 (0000 0000 0100 1101)
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; %si: 74 (0000 0000 0100 1010)
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; %dx: 72 (0000 0000 0100 1000)
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; %dx: 146 (0000 0000 1001 0010)
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; %dx: 2 (0000 0000 0000 0010)
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; %cx: 2 (0000 0000 0000 0010)
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; %di: 52 (0000 0000 0011 0100)
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; %di: 4 (0000 0000 0000 0100)
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; %ax: 4 (0000 0000 0000 0100)
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; Let's pretend that legalizing G_SHL by widening its second
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; source operand is done via G_ANYEXT rather than G_ZEXT and
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; see what happens:
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; addb %sil, %dl
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; %dx: 146 (0000 0000 1001 0010)
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; movl %edx, %ecx
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; %cx: 146 (0000 0000 1001 0010)
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; shlb %cl, %dil
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; %di: 0 (0000 0000 0000 0000)
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; andw $15, %di
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; %di: 0 (0000 0000 0000 0000)
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; movl %edi, %eax
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; %ax: 0 (0000 0000 0000 0000)
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; retq
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}
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