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361 lines
12 KiB
361 lines
12 KiB
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -indvars -S | FileCheck %s
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; PR31181: It may be necessary to drop nuw/nsw flags when moving from a
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; pre-increment comparison to a post-increment comparison.
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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@a = global i32 0
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define i32 @test_drop_nuw() {
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; CHECK-LABEL: @test_drop_nuw(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ -2, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[LOOP]] ]
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; CHECK-NEXT: store i32 [[STOREMERGE]], i32* @a, align 4
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; CHECK-NEXT: [[INC]] = add nsw i32 [[STOREMERGE]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[INC]], 0
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %loop
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loop:
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%storemerge = phi i32 [ -2, %entry ], [ %inc, %loop ]
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store i32 %storemerge, i32* @a
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%cmp = icmp slt i32 %storemerge, -1
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%inc = add nuw nsw i32 %storemerge, 1
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br i1 %cmp, label %loop, label %exit
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exit:
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ret i32 0
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}
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define i32 @test_drop_nsw() {
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; CHECK-LABEL: @test_drop_nsw(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[LOOP]] ]
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; CHECK-NEXT: store i32 [[STOREMERGE]], i32* @a, align 4
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; CHECK-NEXT: [[INC]] = add nuw i32 [[STOREMERGE]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[INC]], -2147483648
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %loop
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loop:
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%storemerge = phi i32 [ 0, %entry ], [ %inc, %loop ]
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store i32 %storemerge, i32* @a
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%cmp = icmp ult i32 %storemerge, 2147483647
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%inc = add nuw nsw i32 %storemerge, 1
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br i1 %cmp, label %loop, label %exit
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exit:
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ret i32 0
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}
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define i32 @test_no_drop_nuw() {
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; CHECK-LABEL: @test_no_drop_nuw(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ -3, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[LOOP]] ]
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; CHECK-NEXT: store i32 [[STOREMERGE]], i32* @a, align 4
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; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[STOREMERGE]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[INC]], -1
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %loop
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loop:
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%storemerge = phi i32 [ -3, %entry ], [ %inc, %loop ]
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store i32 %storemerge, i32* @a
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%cmp = icmp slt i32 %storemerge, -2
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%inc = add nuw nsw i32 %storemerge, 1
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br i1 %cmp, label %loop, label %exit
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exit:
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ret i32 0
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}
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define i32 @test_no_drop_nsw() {
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; CHECK-LABEL: @test_no_drop_nsw(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[LOOP]] ]
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; CHECK-NEXT: store i32 [[STOREMERGE]], i32* @a, align 4
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; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[STOREMERGE]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[INC]], 2147483647
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %loop
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loop:
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%storemerge = phi i32 [ 0, %entry ], [ %inc, %loop ]
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store i32 %storemerge, i32* @a
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%cmp = icmp ult i32 %storemerge, 2147483646
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%inc = add nuw nsw i32 %storemerge, 1
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br i1 %cmp, label %loop, label %exit
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exit:
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ret i32 0
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}
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define i32 @test_no_add_nuw() {
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; CHECK-LABEL: @test_no_add_nuw(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[LOOP]] ]
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; CHECK-NEXT: store i32 [[STOREMERGE]], i32* @a, align 4
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; CHECK-NEXT: [[INC]] = add nsw i32 [[STOREMERGE]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[INC]], 10
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %loop
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loop:
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%storemerge = phi i32 [ -1, %entry ], [ %inc, %loop ]
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store i32 %storemerge, i32* @a
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%cmp = icmp slt i32 %storemerge, 9
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%inc = add i32 %storemerge, 1
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br i1 %cmp, label %loop, label %exit
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exit:
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ret i32 0
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}
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define i32 @test_drop_nsw_var_lim(i32 %lim) {
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; CHECK-LABEL: @test_drop_nsw_var_lim(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[LIM:%.*]], -1
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; CHECK-NEXT: br i1 [[C]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
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; CHECK: loop.preheader:
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[LIM]], 1
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ [[INC:%.*]], [[LOOP]] ], [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: store i32 [[STOREMERGE]], i32* @a, align 4
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; CHECK-NEXT: [[INC]] = add nuw i32 [[STOREMERGE]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[INC]], [[TMP0]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[EXIT_LOOPEXIT:%.*]]
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; CHECK: exit.loopexit:
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%c = icmp ult i32 %lim, -1
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br i1 %c, label %loop, label %exit
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loop:
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%storemerge = phi i32 [ 0, %entry ], [ %inc, %loop ]
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store i32 %storemerge, i32* @a
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%cmp = icmp ult i32 %storemerge, %lim
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%inc = add nuw nsw i32 %storemerge, 1
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br i1 %cmp, label %loop, label %exit
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exit:
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ret i32 0
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}
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; Adopted from D30446.
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; We switch from %iv to %iv2 and need to change nsw to nuw in the process.
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define i32 @switch_to_different_iv_post_inc(i32* %ptr, i1 %always_false) {
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; CHECK-LABEL: @switch_to_different_iv_post_inc(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_COND:%.*]]
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; CHECK: for.cond:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ -2147483648, [[ENTRY:%.*]] ], [ [[IV_INC:%.*]], [[ALWAYS_TAKEN:%.*]] ]
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; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV2_INC:%.*]], [[ALWAYS_TAKEN]] ]
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; CHECK-NEXT: store i32 [[IV]], i32* [[PTR:%.*]], align 4
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; CHECK-NEXT: br i1 [[ALWAYS_FALSE:%.*]], label [[NEVER_TAKEN:%.*]], label [[ALWAYS_TAKEN]]
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; CHECK: never_taken:
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; CHECK-NEXT: store volatile i32 [[IV2]], i32* [[PTR]], align 4
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; CHECK-NEXT: br label [[ALWAYS_TAKEN]]
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; CHECK: always_taken:
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; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], 1
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; CHECK-NEXT: [[IV2_INC]] = add nuw i32 [[IV2]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV2_INC]], -2147483627
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND]], label [[FOR_END:%.*]]
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; CHECK: for.end:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %for.cond
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for.cond:
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%iv = phi i32 [ -2147483648, %entry ], [ %iv.inc, %always_taken ]
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%iv2 = phi i32 [ 0, %entry ], [ %iv2.inc, %always_taken ]
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store i32 %iv, i32* %ptr
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br i1 %always_false, label %never_taken, label %always_taken
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never_taken:
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store volatile i32 %iv2, i32* %ptr
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br label %always_taken
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always_taken:
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%iv.inc = add nsw i32 %iv, 1
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%iv2.inc = add nuw nsw i32 %iv2, 1
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%cmp = icmp slt i32 %iv, 20
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br i1 %cmp, label %for.cond, label %for.end
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for.end:
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ret i32 0
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}
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; Same as previous test case, but with exit block and loop latch being distinct
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; blocks requiring the use of pre-increment.
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define i32 @switch_to_different_iv_pre_inc(i32* %ptr, i1 %always_false) {
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; CHECK-LABEL: @switch_to_different_iv_pre_inc(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_COND:%.*]]
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; CHECK: for.cond:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ -2147483648, [[ENTRY:%.*]] ], [ [[IV_INC:%.*]], [[ALWAYS_TAKEN:%.*]] ]
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; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV2_INC:%.*]], [[ALWAYS_TAKEN]] ]
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; CHECK-NEXT: store i32 [[IV]], i32* [[PTR:%.*]], align 4
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV2]], -2147483628
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: br i1 [[ALWAYS_FALSE:%.*]], label [[NEVER_TAKEN:%.*]], label [[ALWAYS_TAKEN]]
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; CHECK: never_taken:
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; CHECK-NEXT: store volatile i32 [[IV2]], i32* [[PTR]], align 4
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; CHECK-NEXT: br label [[ALWAYS_TAKEN]]
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; CHECK: always_taken:
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; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], 1
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; CHECK-NEXT: [[IV2_INC]] = add nuw i32 [[IV2]], 1
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; CHECK-NEXT: br label [[FOR_COND]]
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; CHECK: for.end:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %for.cond
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for.cond:
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%iv = phi i32 [ -2147483648, %entry ], [ %iv.inc, %always_taken ]
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%iv2 = phi i32 [ 0, %entry ], [ %iv2.inc, %always_taken ]
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store i32 %iv, i32* %ptr
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%cmp = icmp slt i32 %iv, 20
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br i1 %cmp, label %for.body, label %for.end
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for.body:
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br i1 %always_false, label %never_taken, label %always_taken
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never_taken:
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store volatile i32 %iv2, i32* %ptr
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br label %always_taken
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always_taken:
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%iv.inc = add nsw i32 %iv, 1
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%iv2.inc = add nuw nsw i32 %iv2, 1
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br label %for.cond
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for.end:
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ret i32 0
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}
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define i32 @switch_to_different_iv_first_poison(i32* %ptr, i1 %always_false) {
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; CHECK-LABEL: @switch_to_different_iv_first_poison(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_COND:%.*]]
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; CHECK: for.cond:
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; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ -1, [[ENTRY:%.*]] ], [ [[IV2_INC:%.*]], [[ALWAYS_TAKEN:%.*]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ -2147483648, [[ENTRY]] ], [ [[IV_INC:%.*]], [[ALWAYS_TAKEN]] ]
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; CHECK-NEXT: store i32 [[IV]], i32* [[PTR:%.*]], align 4
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; CHECK-NEXT: br i1 [[ALWAYS_FALSE:%.*]], label [[NEVER_TAKEN:%.*]], label [[ALWAYS_TAKEN]]
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; CHECK: never_taken:
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; CHECK-NEXT: store volatile i32 [[IV2]], i32* [[PTR]], align 4
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; CHECK-NEXT: br label [[ALWAYS_TAKEN]]
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; CHECK: always_taken:
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; CHECK-NEXT: [[IV2_INC]] = add nuw nsw i32 [[IV2]], 1
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; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV2_INC]], -2147483628
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND]], label [[FOR_END:%.*]]
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; CHECK: for.end:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %for.cond
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for.cond:
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%iv2 = phi i32 [ -1, %entry ], [ %iv2.inc, %always_taken ]
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%iv = phi i32 [ -2147483648, %entry ], [ %iv.inc, %always_taken ]
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store i32 %iv, i32* %ptr
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br i1 %always_false, label %never_taken, label %always_taken
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never_taken:
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store volatile i32 %iv2, i32* %ptr
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br label %always_taken
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always_taken:
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%iv2.inc = add nuw nsw i32 %iv2, 1
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%iv.inc = add nsw i32 %iv, 1
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%cmp = icmp slt i32 %iv, 20
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br i1 %cmp, label %for.cond, label %for.end
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for.end:
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ret i32 0
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}
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define i32 @switch_to_different_iv_second_poison(i32* %ptr, i1 %always_false) {
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; CHECK-LABEL: @switch_to_different_iv_second_poison(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_COND:%.*]]
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; CHECK: for.cond:
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; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ -2, [[ENTRY:%.*]] ], [ [[IV2_INC:%.*]], [[ALWAYS_TAKEN:%.*]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ -2147483648, [[ENTRY]] ], [ [[IV_INC:%.*]], [[ALWAYS_TAKEN]] ]
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; CHECK-NEXT: store i32 [[IV]], i32* [[PTR:%.*]], align 4
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; CHECK-NEXT: br i1 [[ALWAYS_FALSE:%.*]], label [[NEVER_TAKEN:%.*]], label [[ALWAYS_TAKEN]]
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; CHECK: never_taken:
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; CHECK-NEXT: store volatile i32 [[IV2]], i32* [[PTR]], align 4
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; CHECK-NEXT: br label [[ALWAYS_TAKEN]]
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; CHECK: always_taken:
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; CHECK-NEXT: [[IV2_INC]] = add nsw i32 [[IV2]], 1
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; CHECK-NEXT: [[IV_INC]] = add nsw i32 [[IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i32 [[IV2_INC]], -2147483629
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_COND]], label [[FOR_END:%.*]]
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; CHECK: for.end:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %for.cond
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for.cond:
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%iv2 = phi i32 [ -2, %entry ], [ %iv2.inc, %always_taken ]
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%iv = phi i32 [ -2147483648, %entry ], [ %iv.inc, %always_taken ]
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store i32 %iv, i32* %ptr
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br i1 %always_false, label %never_taken, label %always_taken
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never_taken:
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store volatile i32 %iv2, i32* %ptr
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br label %always_taken
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always_taken:
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%iv2.inc = add nuw nsw i32 %iv2, 1
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%iv.inc = add nsw i32 %iv, 1
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%cmp = icmp slt i32 %iv, 20
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br i1 %cmp, label %for.cond, label %for.end
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for.end:
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ret i32 0
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}
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