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240 lines
9.3 KiB
240 lines
9.3 KiB
//===-- MCInstrDescView.h ---------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// Provide views around LLVM structures to represents an instruction instance,
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/// as well as its implicit and explicit arguments in a uniform way.
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/// Arguments that are explicit and independant (non tied) also have a Variable
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/// associated to them so the instruction can be fully defined by reading its
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/// Variables.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H
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#define LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H
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#include <memory>
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#include <random>
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#include <unordered_map>
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#include "RegisterAliasing.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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namespace llvm {
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namespace exegesis {
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// A variable represents the value associated to an Operand or a set of Operands
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// if they are tied together.
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struct Variable {
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// Returns the index of this Variable inside Instruction's Variable.
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unsigned getIndex() const;
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// Returns the index of the Operand linked to this Variable.
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unsigned getPrimaryOperandIndex() const;
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// Returns whether this Variable has more than one Operand linked to it.
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bool hasTiedOperands() const;
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// The indices of the operands tied to this Variable.
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SmallVector<unsigned, 2> TiedOperands;
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// The index of this Variable in Instruction.Variables and its associated
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// Value in InstructionBuilder.VariableValues.
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Optional<uint8_t> Index;
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};
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// MCOperandInfo can only represents Explicit operands. This object gives a
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// uniform view of Implicit and Explicit Operands.
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// - Index: can be used to refer to MCInstrDesc::operands for Explicit operands.
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// - Tracker: is set for Register Operands and is used to keep track of possible
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// registers and the registers reachable from them (aliasing registers).
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// - Info: a shortcut for MCInstrDesc::operands()[Index].
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// - TiedToIndex: the index of the Operand holding the value or -1.
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// - ImplicitReg: a pointer to the register value when Operand is Implicit,
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// nullptr otherwise.
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// - VariableIndex: the index of the Variable holding the value for this Operand
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// or -1 if this operand is implicit.
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struct Operand {
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bool isExplicit() const;
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bool isImplicit() const;
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bool isImplicitReg() const;
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bool isDef() const;
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bool isUse() const;
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bool isReg() const;
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bool isTied() const;
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bool isVariable() const;
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bool isMemory() const;
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bool isImmediate() const;
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unsigned getIndex() const;
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unsigned getTiedToIndex() const;
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unsigned getVariableIndex() const;
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unsigned getImplicitReg() const;
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const RegisterAliasingTracker &getRegisterAliasing() const;
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const MCOperandInfo &getExplicitOperandInfo() const;
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// Please use the accessors above and not the following fields.
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Optional<uint8_t> Index;
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bool IsDef = false;
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const RegisterAliasingTracker *Tracker = nullptr; // Set for Register Op.
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const MCOperandInfo *Info = nullptr; // Set for Explicit Op.
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Optional<uint8_t> TiedToIndex; // Set for Reg&Explicit Op.
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const MCPhysReg *ImplicitReg = nullptr; // Set for Implicit Op.
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Optional<uint8_t> VariableIndex; // Set for Explicit Op.
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};
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/// A cache of BitVector to reuse between Instructions.
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/// The cache will only be exercised during Instruction initialization.
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/// For X86, this is ~160 unique vectors for all of the ~15K Instructions.
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struct BitVectorCache {
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// Finds or allocates the provided BitVector in the cache and retrieves it's
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// unique instance.
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const BitVector *getUnique(BitVector &&BV) const;
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private:
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mutable std::vector<std::unique_ptr<BitVector>> Cache;
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};
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// A view over an MCInstrDesc offering a convenient interface to compute
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// Register aliasing.
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struct Instruction {
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// Create an instruction for a particular Opcode.
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static std::unique_ptr<Instruction>
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create(const MCInstrInfo &InstrInfo, const RegisterAliasingTrackerCache &RATC,
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const BitVectorCache &BVC, unsigned Opcode);
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// Prevent copy or move, instructions are allocated once and cached.
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Instruction(const Instruction &) = delete;
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Instruction(Instruction &&) = delete;
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Instruction &operator=(const Instruction &) = delete;
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Instruction &operator=(Instruction &&) = delete;
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// Returns the Operand linked to this Variable.
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// In case the Variable is tied, the primary (i.e. Def) Operand is returned.
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const Operand &getPrimaryOperand(const Variable &Var) const;
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// Whether this instruction is self aliasing through its tied registers.
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// Repeating this instruction is guaranteed to executes sequentially.
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bool hasTiedRegisters() const;
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// Whether this instruction is self aliasing through its implicit registers.
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// Repeating this instruction is guaranteed to executes sequentially.
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bool hasAliasingImplicitRegisters() const;
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// Whether this instruction is self aliasing through some registers.
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// Repeating this instruction may execute sequentially by picking aliasing
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// Use and Def registers. It may also execute in parallel by picking non
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// aliasing Use and Def registers.
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bool hasAliasingRegisters(const BitVector &ForbiddenRegisters) const;
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// Whether this instruction's registers alias with OtherInstr's registers.
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bool hasAliasingRegistersThrough(const Instruction &OtherInstr,
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const BitVector &ForbiddenRegisters) const;
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// Returns whether this instruction has Memory Operands.
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// Repeating this instruction executes sequentially with an instruction that
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// reads or write the same memory region.
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bool hasMemoryOperands() const;
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// Returns whether this instruction as at least one use or one def.
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// Repeating this instruction may execute sequentially by adding an
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// instruction that aliases one of these.
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bool hasOneUseOrOneDef() const;
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// Convenient function to help with debugging.
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void dump(const MCRegisterInfo &RegInfo,
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const RegisterAliasingTrackerCache &RATC,
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raw_ostream &Stream) const;
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const MCInstrDesc &Description;
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const StringRef Name; // The name of this instruction.
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const SmallVector<Operand, 8> Operands;
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const SmallVector<Variable, 4> Variables;
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const BitVector &ImplDefRegs; // The set of aliased implicit def registers.
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const BitVector &ImplUseRegs; // The set of aliased implicit use registers.
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const BitVector &AllDefRegs; // The set of all aliased def registers.
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const BitVector &AllUseRegs; // The set of all aliased use registers.
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private:
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Instruction(const MCInstrDesc *Description, StringRef Name,
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SmallVector<Operand, 8> Operands,
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SmallVector<Variable, 4> Variables, const BitVector *ImplDefRegs,
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const BitVector *ImplUseRegs, const BitVector *AllDefRegs,
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const BitVector *AllUseRegs);
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};
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// Instructions are expensive to instantiate. This class provides a cache of
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// Instructions with lazy construction.
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struct InstructionsCache {
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InstructionsCache(const MCInstrInfo &InstrInfo,
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const RegisterAliasingTrackerCache &RATC);
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// Returns the Instruction object corresponding to this Opcode.
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const Instruction &getInstr(unsigned Opcode) const;
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private:
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const MCInstrInfo &InstrInfo;
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const RegisterAliasingTrackerCache &RATC;
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mutable std::unordered_map<unsigned, std::unique_ptr<Instruction>>
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Instructions;
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const BitVectorCache BVC;
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};
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// Represents the assignment of a Register to an Operand.
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struct RegisterOperandAssignment {
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RegisterOperandAssignment(const Operand *Operand, MCPhysReg Reg)
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: Op(Operand), Reg(Reg) {}
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const Operand *Op; // Pointer to an Explicit Register Operand.
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MCPhysReg Reg;
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bool operator==(const RegisterOperandAssignment &other) const;
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};
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// Represents a set of Operands that would alias through the use of some
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// Registers.
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// There are two reasons why operands would alias:
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// - The registers assigned to each of the operands are the same or alias each
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// other (e.g. AX/AL)
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// - The operands are tied.
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struct AliasingRegisterOperands {
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SmallVector<RegisterOperandAssignment, 1> Defs; // Unlikely size() > 1.
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SmallVector<RegisterOperandAssignment, 2> Uses;
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// True is Defs and Use contain an Implicit Operand.
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bool hasImplicitAliasing() const;
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bool operator==(const AliasingRegisterOperands &other) const;
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};
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// Returns all possible configurations leading Def registers of DefInstruction
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// to alias with Use registers of UseInstruction.
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struct AliasingConfigurations {
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AliasingConfigurations(const Instruction &DefInstruction,
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const Instruction &UseInstruction);
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bool empty() const; // True if no aliasing configuration is found.
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bool hasImplicitAliasing() const;
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SmallVector<AliasingRegisterOperands, 32> Configurations;
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};
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// Writes MCInst to OS.
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// This is not assembly but the internal LLVM's name for instructions and
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// registers.
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void DumpMCInst(const MCRegisterInfo &MCRegisterInfo,
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const MCInstrInfo &MCInstrInfo, const MCInst &MCInst,
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raw_ostream &OS);
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} // namespace exegesis
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} // namespace llvm
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#endif // LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H
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