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276 lines
10 KiB
276 lines
10 KiB
//===-- SnippetGenerator.cpp ------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include <array>
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#include <string>
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#include "Assembler.h"
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#include "Error.h"
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#include "MCInstrDescView.h"
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#include "SnippetGenerator.h"
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#include "Target.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/FileSystem.h"
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#include "llvm/Support/FormatVariadic.h"
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#include "llvm/Support/Program.h"
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namespace llvm {
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namespace exegesis {
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std::vector<CodeTemplate> getSingleton(CodeTemplate &&CT) {
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std::vector<CodeTemplate> Result;
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Result.push_back(std::move(CT));
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return Result;
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}
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SnippetGeneratorFailure::SnippetGeneratorFailure(const Twine &S)
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: StringError(S, inconvertibleErrorCode()) {}
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SnippetGenerator::SnippetGenerator(const LLVMState &State, const Options &Opts)
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: State(State), Opts(Opts) {}
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SnippetGenerator::~SnippetGenerator() = default;
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Error SnippetGenerator::generateConfigurations(
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const InstructionTemplate &Variant, std::vector<BenchmarkCode> &Benchmarks,
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const BitVector &ExtraForbiddenRegs) const {
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BitVector ForbiddenRegs = State.getRATC().reservedRegisters();
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ForbiddenRegs |= ExtraForbiddenRegs;
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// If the instruction has memory registers, prevent the generator from
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// using the scratch register and its aliasing registers.
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if (Variant.getInstr().hasMemoryOperands()) {
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const auto &ET = State.getExegesisTarget();
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unsigned ScratchSpacePointerInReg =
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ET.getScratchMemoryRegister(State.getTargetMachine().getTargetTriple());
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if (ScratchSpacePointerInReg == 0)
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return make_error<Failure>(
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"Infeasible : target does not support memory instructions");
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const auto &ScratchRegAliases =
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State.getRATC().getRegister(ScratchSpacePointerInReg).aliasedBits();
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// If the instruction implicitly writes to ScratchSpacePointerInReg , abort.
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// FIXME: We could make a copy of the scratch register.
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for (const auto &Op : Variant.getInstr().Operands) {
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if (Op.isDef() && Op.isImplicitReg() &&
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ScratchRegAliases.test(Op.getImplicitReg()))
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return make_error<Failure>(
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"Infeasible : memory instruction uses scratch memory register");
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}
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ForbiddenRegs |= ScratchRegAliases;
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}
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if (auto E = generateCodeTemplates(Variant, ForbiddenRegs)) {
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MutableArrayRef<CodeTemplate> Templates = E.get();
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// Avoid reallocations in the loop.
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Benchmarks.reserve(Benchmarks.size() + Templates.size());
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for (CodeTemplate &CT : Templates) {
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// TODO: Generate as many BenchmarkCode as needed.
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{
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BenchmarkCode BC;
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BC.Info = CT.Info;
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for (InstructionTemplate &IT : CT.Instructions) {
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if (auto error = randomizeUnsetVariables(State, ForbiddenRegs, IT))
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return error;
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BC.Key.Instructions.push_back(IT.build());
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}
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if (CT.ScratchSpacePointerInReg)
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BC.LiveIns.push_back(CT.ScratchSpacePointerInReg);
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BC.Key.RegisterInitialValues =
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computeRegisterInitialValues(CT.Instructions);
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BC.Key.Config = CT.Config;
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Benchmarks.emplace_back(std::move(BC));
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if (Benchmarks.size() >= Opts.MaxConfigsPerOpcode) {
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// We reached the number of allowed configs and return early.
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return Error::success();
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}
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}
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}
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return Error::success();
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} else
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return E.takeError();
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}
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std::vector<RegisterValue> SnippetGenerator::computeRegisterInitialValues(
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const std::vector<InstructionTemplate> &Instructions) const {
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// Collect all register uses and create an assignment for each of them.
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// Ignore memory operands which are handled separately.
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// Loop invariant: DefinedRegs[i] is true iif it has been set at least once
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// before the current instruction.
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BitVector DefinedRegs = State.getRATC().emptyRegisters();
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std::vector<RegisterValue> RIV;
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for (const InstructionTemplate &IT : Instructions) {
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// Returns the register that this Operand sets or uses, or 0 if this is not
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// a register.
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const auto GetOpReg = [&IT](const Operand &Op) -> unsigned {
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if (Op.isMemory())
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return 0;
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if (Op.isImplicitReg())
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return Op.getImplicitReg();
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if (Op.isExplicit() && IT.getValueFor(Op).isReg())
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return IT.getValueFor(Op).getReg();
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return 0;
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};
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// Collect used registers that have never been def'ed.
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for (const Operand &Op : IT.getInstr().Operands) {
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if (Op.isUse()) {
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const unsigned Reg = GetOpReg(Op);
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if (Reg > 0 && !DefinedRegs.test(Reg)) {
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RIV.push_back(RegisterValue::zero(Reg));
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DefinedRegs.set(Reg);
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}
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}
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}
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// Mark defs as having been def'ed.
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for (const Operand &Op : IT.getInstr().Operands) {
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if (Op.isDef()) {
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const unsigned Reg = GetOpReg(Op);
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if (Reg > 0)
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DefinedRegs.set(Reg);
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}
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}
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}
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return RIV;
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}
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Expected<std::vector<CodeTemplate>>
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generateSelfAliasingCodeTemplates(InstructionTemplate Variant) {
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const AliasingConfigurations SelfAliasing(Variant.getInstr(),
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Variant.getInstr());
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if (SelfAliasing.empty())
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return make_error<SnippetGeneratorFailure>("empty self aliasing");
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std::vector<CodeTemplate> Result;
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Result.emplace_back();
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CodeTemplate &CT = Result.back();
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if (SelfAliasing.hasImplicitAliasing()) {
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CT.Info = "implicit Self cycles, picking random values.";
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} else {
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CT.Info = "explicit self cycles, selecting one aliasing Conf.";
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// This is a self aliasing instruction so defs and uses are from the same
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// instance, hence twice Variant in the following call.
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setRandomAliasing(SelfAliasing, Variant, Variant);
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}
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CT.Instructions.push_back(std::move(Variant));
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return std::move(Result);
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}
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Expected<std::vector<CodeTemplate>>
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generateUnconstrainedCodeTemplates(const InstructionTemplate &Variant,
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StringRef Msg) {
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std::vector<CodeTemplate> Result;
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Result.emplace_back();
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CodeTemplate &CT = Result.back();
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CT.Info =
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std::string(formatv("{0}, repeating an unconstrained assignment", Msg));
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CT.Instructions.push_back(std::move(Variant));
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return std::move(Result);
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}
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std::mt19937 &randomGenerator() {
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static std::random_device RandomDevice;
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static std::mt19937 RandomGenerator(RandomDevice());
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return RandomGenerator;
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}
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size_t randomIndex(size_t Max) {
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std::uniform_int_distribution<> Distribution(0, Max);
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return Distribution(randomGenerator());
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}
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template <typename C> static decltype(auto) randomElement(const C &Container) {
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assert(!Container.empty() &&
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"Can't pick a random element from an empty container)");
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return Container[randomIndex(Container.size() - 1)];
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}
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static void setRegisterOperandValue(const RegisterOperandAssignment &ROV,
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InstructionTemplate &IB) {
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assert(ROV.Op);
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if (ROV.Op->isExplicit()) {
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auto &AssignedValue = IB.getValueFor(*ROV.Op);
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if (AssignedValue.isValid()) {
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assert(AssignedValue.isReg() && AssignedValue.getReg() == ROV.Reg);
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return;
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}
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AssignedValue = MCOperand::createReg(ROV.Reg);
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} else {
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assert(ROV.Op->isImplicitReg());
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assert(ROV.Reg == ROV.Op->getImplicitReg());
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}
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}
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size_t randomBit(const BitVector &Vector) {
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assert(Vector.any());
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auto Itr = Vector.set_bits_begin();
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for (size_t I = randomIndex(Vector.count() - 1); I != 0; --I)
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++Itr;
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return *Itr;
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}
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void setRandomAliasing(const AliasingConfigurations &AliasingConfigurations,
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InstructionTemplate &DefIB, InstructionTemplate &UseIB) {
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assert(!AliasingConfigurations.empty());
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assert(!AliasingConfigurations.hasImplicitAliasing());
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const auto &RandomConf = randomElement(AliasingConfigurations.Configurations);
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setRegisterOperandValue(randomElement(RandomConf.Defs), DefIB);
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setRegisterOperandValue(randomElement(RandomConf.Uses), UseIB);
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}
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static Error randomizeMCOperand(const LLVMState &State,
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const Instruction &Instr, const Variable &Var,
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MCOperand &AssignedValue,
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const BitVector &ForbiddenRegs) {
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const Operand &Op = Instr.getPrimaryOperand(Var);
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if (Op.getExplicitOperandInfo().OperandType >=
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MCOI::OperandType::OPERAND_FIRST_TARGET)
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return State.getExegesisTarget().randomizeTargetMCOperand(
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Instr, Var, AssignedValue, ForbiddenRegs);
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switch (Op.getExplicitOperandInfo().OperandType) {
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case MCOI::OperandType::OPERAND_IMMEDIATE:
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// FIXME: explore immediate values too.
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AssignedValue = MCOperand::createImm(1);
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break;
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case MCOI::OperandType::OPERAND_REGISTER: {
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assert(Op.isReg());
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auto AllowedRegs = Op.getRegisterAliasing().sourceBits();
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assert(AllowedRegs.size() == ForbiddenRegs.size());
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for (auto I : ForbiddenRegs.set_bits())
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AllowedRegs.reset(I);
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if (!AllowedRegs.any())
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return make_error<Failure>(
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Twine("no available registers:\ncandidates:\n")
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.concat(debugString(State.getRegInfo(),
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Op.getRegisterAliasing().sourceBits()))
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.concat("\nforbidden:\n")
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.concat(debugString(State.getRegInfo(), ForbiddenRegs)));
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AssignedValue = MCOperand::createReg(randomBit(AllowedRegs));
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break;
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}
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default:
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break;
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}
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return Error::success();
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}
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Error randomizeUnsetVariables(const LLVMState &State,
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const BitVector &ForbiddenRegs,
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InstructionTemplate &IT) {
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for (const Variable &Var : IT.getInstr().Variables) {
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MCOperand &AssignedValue = IT.getValueFor(Var);
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if (!AssignedValue.isValid())
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if (auto Err = randomizeMCOperand(State, IT.getInstr(), Var,
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AssignedValue, ForbiddenRegs))
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return Err;
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}
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return Error::success();
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}
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} // namespace exegesis
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} // namespace llvm
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