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176 lines
11 KiB
176 lines
11 KiB
; RUN: opt %loadPolly -polly-opt-isl -polly-pattern-matching-based-opts=true \
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; RUN: -polly-target-throughput-vector-fma=1 \
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; RUN: -polly-target-latency-vector-fma=8 \
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; RUN: -analyze -polly-ast -polly-target-1st-cache-level-associativity=8 \
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; RUN: -polly-target-2nd-cache-level-associativity=8 \
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; RUN: -polly-target-1st-cache-level-size=32768 \
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; RUN: -polly-target-vector-register-bitwidth=256 \
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; RUN: -polly-target-2nd-cache-level-size=262144 < %s \
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; RUN: | FileCheck %s
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;
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; opt %loadPolly -polly-opt-isl -polly-pattern-matching-based-opts=true \
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; -polly-target-throughput-vector-fma=1 \
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; -polly-target-latency-vector-fma=8 \
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; -polly-codegen -polly-target-1st-cache-level-associativity=8 \
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; -polly-target-2nd-cache-level-associativity=8 \
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; -polly-target-1st-cache-level-size=32768 \
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; -polly-target-vector-register-bitwidth=256 \
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; -polly-target-2nd-cache-level-size=262144 -gvn -licm -slp-vectorizer \
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; -mcpu=corei7 -stats -S < %s 2>&1 | FileCheck %s \
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; --check-prefix=AUTO-VECTORIZATION
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;
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;
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; /* We isolate a set of partial tile prefixes, which contains only partial
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; tile prefixes that have exactly Mr x Nr iterations of the two innermost
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; loops produced by the optimization of the matrix multiplication. Mr and
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; Nr are parameters of the micro-kernel (see getMicroKernelParams and
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; getMacroKernelParams from lib/Transform/ScheduleOptimizer.cpp for
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; details). This test check that in case it cannot be proved that
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; the number of loop iterations can be evenly divided by tile sizes
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; and we tile and unroll the point loops, it helps to get rid of
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; the conditional expressions of the unrolled innermost loops, which
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; prevents stores and loads of the unrolled loops from being sunk
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; and hoisted. Otherwise, it causes a run-time regression in comparison
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; to the vectorized code with sunk and hoisted memory accesses. */
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; /* C := A * B + C */
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; for (i = 0; i < 1020; i++)
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; for (j = 0; j < 1020; j++)
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; for (k = 0; k < 1020; ++k)
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; C[i][j] += A[i][k] * B[k][j];
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;
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; CHECK: // 1st level tiling - Tiles
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; CHECK-NEXT: for (int c1 = 0; c1 <= 3; c1 += 1) {
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; CHECK-NEXT: for (int c3 = 0; c3 <= 1019; c3 += 1)
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; CHECK-NEXT: for (int c4 = 256 * c1; c4 <= min(1019, 256 * c1 + 255); c4 += 1)
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; CHECK-NEXT: CopyStmt_0(0, c3, c4);
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; CHECK-NEXT: for (int c2 = 0; c2 <= 10; c2 += 1) {
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; CHECK-NEXT: for (int c3 = 96 * c2; c3 <= min(1019, 96 * c2 + 95); c3 += 1)
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; CHECK-NEXT: for (int c5 = 256 * c1; c5 <= min(1019, 256 * c1 + 255); c5 += 1)
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; CHECK-NEXT: CopyStmt_1(c3, 0, c5);
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; CHECK-NEXT: // 1st level tiling - Points
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; CHECK-NEXT: // Register tiling - Tiles
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; CHECK-NEXT: {
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; CHECK-NEXT: for (int c3 = 0; c3 <= 126; c3 += 1)
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; CHECK-NEXT: for (int c4 = 0; c4 <= min(23, -24 * c2 + 254); c4 += 1)
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; CHECK-NEXT: for (int c5 = 0; c5 <= min(255, -256 * c1 + 1019); c5 += 1) {
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; CHECK-NEXT: // Loop Vectorizer Disabled
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; CHECK-NEXT: // Register tiling - Points
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; CHECK-NEXT: {
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 1, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 2, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 3, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 4, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 5, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 6, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 8 * c3 + 7, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 1, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 2, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 3, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 4, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 5, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 6, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 8 * c3 + 7, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 1, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 2, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 3, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 4, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 5, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 6, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 8 * c3 + 7, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 1, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 2, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 3, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 4, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 5, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 6, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 8 * c3 + 7, 256 * c1 + c5);
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; CHECK-NEXT: }
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; CHECK-NEXT: }
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; CHECK-NEXT: for (int c4 = 0; c4 <= min(23, -24 * c2 + 254); c4 += 1)
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; CHECK-NEXT: for (int c5 = 0; c5 <= min(255, -256 * c1 + 1019); c5 += 1) {
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; CHECK-NEXT: // Loop Vectorizer Disabled
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; CHECK-NEXT: // Register tiling - Points
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; CHECK-NEXT: {
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 1016, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 1017, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 1018, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4, 1019, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 1016, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 1017, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 1018, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 1, 1019, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 1016, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 1017, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 1018, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 2, 1019, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 1016, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 1017, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 1018, 256 * c1 + c5);
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; CHECK-NEXT: Stmt_for_body6(96 * c2 + 4 * c4 + 3, 1019, 256 * c1 + c5);
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; CHECK-NEXT: }
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; CHECK-NEXT: }
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; CHECK-NEXT: }
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; CHECK-NEXT: }
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; CHECK-NEXT: }
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;
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; AUTO-VECTORIZATION: fmul <4 x double>
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; AUTO-VECTORIZATION: fadd <4 x double>
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; AUTO-VECTORIZATION: 36 SLP - Number of vector instructions generated
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; AUTO-VECTORIZATION: 146 licm - Number of instructions hoisted out of loop
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; AUTO-VECTORIZATION: 1 licm - Number of load insts hoisted or sunk
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; AUTO-VECTORIZATION: 32 licm - Number of memory locations promoted to registers
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;
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-unknown"
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define internal void @kernel_gemm(i32 %ni, i32 %nj, i32 %nk, double %alpha, double %beta, [1020 x double]* %C, [1020 x double]* %A, [1020 x double]* %B) #0 {
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entry:
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br label %entry.split
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entry.split: ; preds = %entry
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br label %for.cond1.preheader
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for.cond1.preheader: ; preds = %for.inc20, %entry.split
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%indvars.iv41 = phi i64 [ 0, %entry.split ], [ %indvars.iv.next42, %for.inc20 ]
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br label %for.cond4.preheader
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for.cond4.preheader: ; preds = %for.inc17, %for.cond1.preheader
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%indvars.iv38 = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next39, %for.inc17 ]
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br label %for.body6
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for.body6: ; preds = %for.body6, %for.cond4.preheader
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%indvars.iv = phi i64 [ 0, %for.cond4.preheader ], [ %indvars.iv.next, %for.body6 ]
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%arrayidx8 = getelementptr inbounds [1020 x double], [1020 x double]* %A, i64 %indvars.iv41, i64 %indvars.iv
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%tmp = load double, double* %arrayidx8, align 8
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%arrayidx12 = getelementptr inbounds [1020 x double], [1020 x double]* %B, i64 %indvars.iv, i64 %indvars.iv38
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%tmp1 = load double, double* %arrayidx12, align 8
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%mul = fmul double %tmp, %tmp1
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%arrayidx16 = getelementptr inbounds [1020 x double], [1020 x double]* %C, i64 %indvars.iv41, i64 %indvars.iv38
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%tmp2 = load double, double* %arrayidx16, align 8
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%add = fadd double %tmp2, %mul
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store double %add, double* %arrayidx16, align 8
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp ne i64 %indvars.iv.next, 1020
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br i1 %exitcond, label %for.body6, label %for.inc17
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for.inc17: ; preds = %for.body6
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%indvars.iv.next39 = add nuw nsw i64 %indvars.iv38, 1
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%exitcond40 = icmp ne i64 %indvars.iv.next39, 1020
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br i1 %exitcond40, label %for.cond4.preheader, label %for.inc20
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for.inc20: ; preds = %for.inc17
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%indvars.iv.next42 = add nuw nsw i64 %indvars.iv41, 1
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%exitcond43 = icmp ne i64 %indvars.iv.next42, 1020
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br i1 %exitcond43, label %for.cond1.preheader, label %for.end22
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for.end22: ; preds = %for.inc20
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ret void
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}
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attributes #0 = { nounwind uwtable "target-cpu"="x86-64" "target-features"="+aes,+avx,+cmov,+cx16,+fxsr,+mmx,+pclmul,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" }
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