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699 lines
21 KiB
699 lines
21 KiB
/*
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* Copyright 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#ifdef DRV_I915
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#include <assert.h>
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#include <errno.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <string.h>
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#include <sys/mman.h>
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#include <unistd.h>
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#include <xf86drm.h>
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#include "drv_priv.h"
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#include "external/i915_drm.h"
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#include "helpers.h"
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#include "util.h"
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#define I915_CACHELINE_SIZE 64
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#define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
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static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888,
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DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888,
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DRM_FORMAT_RGB565, DRM_FORMAT_XBGR2101010,
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DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB2101010,
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DRM_FORMAT_XRGB8888 };
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static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F };
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static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
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DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
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static const uint64_t gen_modifier_order[] = { I915_FORMAT_MOD_Y_TILED_CCS, I915_FORMAT_MOD_Y_TILED,
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I915_FORMAT_MOD_X_TILED, DRM_FORMAT_MOD_LINEAR };
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static const uint64_t gen11_modifier_order[] = { I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
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DRM_FORMAT_MOD_LINEAR };
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struct modifier_support_t {
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const uint64_t *order;
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uint32_t count;
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};
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struct i915_device {
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uint32_t gen;
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int32_t has_llc;
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int32_t has_hw_protection;
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struct modifier_support_t modifier;
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int device_id;
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bool is_adlp;
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};
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static void i915_info_from_device_id(struct i915_device *i915)
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{
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const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
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0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
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const uint16_t gen11_ids[] = { 0x4E71, 0x4E61, 0x4E51, 0x4E55, 0x4E57 };
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const uint16_t gen12_ids[] = { 0x9A40, 0x9A49, 0x9A59, 0x9A60, 0x9A68, 0x9A70,
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0x9A78, 0x9AC0, 0x9AC9, 0x9AD9, 0x9AF8 };
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const uint16_t adlp_ids[] = { 0x46A0, 0x46A1, 0x46A2, 0x46A3, 0x46A6,
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0x46A8, 0x46AA, 0x462A, 0x4626, 0x4628,
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0x46B0, 0x46B1, 0x46B2, 0x46B3, 0x46C0,
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0x46C1, 0x46C2, 0x46C3 };
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unsigned i;
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i915->gen = 4;
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i915->is_adlp = false;
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for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
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if (gen3_ids[i] == i915->device_id)
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i915->gen = 3;
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/* Gen 11 */
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for (i = 0; i < ARRAY_SIZE(gen11_ids); i++)
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if (gen11_ids[i] == i915->device_id)
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i915->gen = 11;
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/* Gen 12 */
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for (i = 0; i < ARRAY_SIZE(gen12_ids); i++)
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if (gen12_ids[i] == i915->device_id)
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i915->gen = 12;
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for (i = 0; i < ARRAY_SIZE(adlp_ids); i++)
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if (adlp_ids[i] == i915->device_id) {
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i915->is_adlp = true;
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i915->gen = 12;
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}
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}
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static void i915_get_modifier_order(struct i915_device *i915)
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{
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if (i915->gen == 11) {
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i915->modifier.order = gen11_modifier_order;
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i915->modifier.count = ARRAY_SIZE(gen11_modifier_order);
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} else {
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i915->modifier.order = gen_modifier_order;
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i915->modifier.count = ARRAY_SIZE(gen_modifier_order);
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}
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}
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static uint64_t unset_flags(uint64_t current_flags, uint64_t mask)
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{
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uint64_t value = current_flags & ~mask;
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return value;
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}
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static int i915_add_combinations(struct driver *drv)
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{
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struct i915_device *i915 = drv->priv;
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const uint64_t scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT;
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const uint64_t render = BO_USE_RENDER_MASK;
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const uint64_t texture_only = BO_USE_TEXTURE_MASK;
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// HW protected buffers also need to be scanned out.
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const uint64_t hw_protected =
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i915->has_hw_protection ? (BO_USE_PROTECTED | BO_USE_SCANOUT) : 0;
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const uint64_t linear_mask = BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN |
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BO_USE_SW_WRITE_OFTEN | BO_USE_SW_READ_RARELY |
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BO_USE_SW_WRITE_RARELY;
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struct format_metadata metadata_linear = { .tiling = I915_TILING_NONE,
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.priority = 1,
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.modifier = DRM_FORMAT_MOD_LINEAR };
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drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
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&metadata_linear, scanout_and_render);
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drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata_linear,
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render);
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drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats),
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&metadata_linear, texture_only);
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drv_modify_linear_combinations(drv);
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/* NV12 format for camera, display, decoding and encoding. */
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/* IPU3 camera ISP supports only NV12 output. */
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drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata_linear,
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BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
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BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER |
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hw_protected);
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/* Android CTS tests require this. */
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drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata_linear, BO_USE_SW_MASK);
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/*
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* R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
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* from camera and input/output from hardware decoder/encoder.
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*/
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drv_modify_combination(drv, DRM_FORMAT_R8, &metadata_linear,
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BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
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BO_USE_HW_VIDEO_ENCODER);
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const uint64_t render_not_linear = unset_flags(render, linear_mask);
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const uint64_t scanout_and_render_not_linear = render_not_linear | BO_USE_SCANOUT;
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struct format_metadata metadata_x_tiled = { .tiling = I915_TILING_X,
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.priority = 2,
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.modifier = I915_FORMAT_MOD_X_TILED };
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drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata_x_tiled,
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render_not_linear);
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drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
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&metadata_x_tiled, scanout_and_render_not_linear);
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struct format_metadata metadata_y_tiled = { .tiling = I915_TILING_Y,
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.priority = 3,
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.modifier = I915_FORMAT_MOD_Y_TILED };
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/* Support y-tiled NV12 and P010 for libva */
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#ifdef I915_SCANOUT_Y_TILED
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const uint64_t nv12_usage =
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BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT | hw_protected;
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const uint64_t p010_usage = BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | hw_protected |
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(i915->gen >= 11 ? BO_USE_SCANOUT : 0);
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#else
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const uint64_t nv12_usage = BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER;
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const uint64_t p010_usage = nv12_usage;
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#endif
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drv_add_combination(drv, DRM_FORMAT_NV12, &metadata_y_tiled, nv12_usage);
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drv_add_combination(drv, DRM_FORMAT_P010, &metadata_y_tiled, p010_usage);
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drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata_y_tiled,
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render_not_linear);
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// Y-tiled scanout isn't available on old platforms so we add
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// |scanout_render_formats| without that USE flag.
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drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
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&metadata_y_tiled, render_not_linear);
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return 0;
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}
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static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
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uint32_t *aligned_height)
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{
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struct i915_device *i915 = bo->drv->priv;
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uint32_t horizontal_alignment;
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uint32_t vertical_alignment;
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switch (tiling) {
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default:
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case I915_TILING_NONE:
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/*
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* The Intel GPU doesn't need any alignment in linear mode,
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* but libva requires the allocation stride to be aligned to
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* 16 bytes and height to 4 rows. Further, we round up the
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* horizontal alignment so that row start on a cache line (64
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* bytes).
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*/
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#ifdef LINEAR_ALIGN_256
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/*
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* If we want to import these buffers to amdgpu they need to
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* their match LINEAR_ALIGNED requirement of 256 byte alignement.
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*/
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horizontal_alignment = 256;
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#else
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horizontal_alignment = 64;
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#endif
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vertical_alignment = 4;
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break;
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case I915_TILING_X:
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horizontal_alignment = 512;
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vertical_alignment = 8;
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break;
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case I915_TILING_Y:
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if (i915->gen == 3) {
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horizontal_alignment = 512;
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vertical_alignment = 8;
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} else {
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horizontal_alignment = 128;
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vertical_alignment = 32;
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}
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break;
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}
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*aligned_height = ALIGN(*aligned_height, vertical_alignment);
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if (i915->gen > 3) {
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*stride = ALIGN(*stride, horizontal_alignment);
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} else {
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while (*stride > horizontal_alignment)
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horizontal_alignment <<= 1;
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*stride = horizontal_alignment;
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}
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/* stride must be power-of-two aligned for ADL-P tiled buffers*/
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if (i915->is_adlp && (*stride > 1) && (tiling != I915_TILING_NONE))
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*stride = 1 << (32 - __builtin_clz(*stride -1));
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if (i915->gen <= 3 && *stride > 8192)
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return -EINVAL;
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return 0;
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}
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static void i915_clflush(void *start, size_t size)
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{
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void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
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void *end = (void *)((uintptr_t)start + size);
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__builtin_ia32_mfence();
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while (p < end) {
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__builtin_ia32_clflush(p);
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p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
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}
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}
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static int i915_init(struct driver *drv)
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{
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int ret;
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struct i915_device *i915;
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drm_i915_getparam_t get_param = { 0 };
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i915 = calloc(1, sizeof(*i915));
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if (!i915)
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return -ENOMEM;
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get_param.param = I915_PARAM_CHIPSET_ID;
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get_param.value = &(i915->device_id);
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ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
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if (ret) {
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drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
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free(i915);
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return -EINVAL;
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}
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/* must call before i915->gen is used anywhere else */
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i915_info_from_device_id(i915);
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i915_get_modifier_order(i915);
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memset(&get_param, 0, sizeof(get_param));
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get_param.param = I915_PARAM_HAS_LLC;
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get_param.value = &i915->has_llc;
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ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
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if (ret) {
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drv_log("Failed to get I915_PARAM_HAS_LLC\n");
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free(i915);
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return -EINVAL;
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}
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if (i915->gen >= 12)
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i915->has_hw_protection = 1;
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drv->priv = i915;
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return i915_add_combinations(drv);
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}
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/*
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* Returns true if the height of a buffer of the given format should be aligned
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* to the largest coded unit (LCU) assuming that it will be used for video. This
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* is based on gmmlib's GmmIsYUVFormatLCUAligned().
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*/
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static bool i915_format_needs_LCU_alignment(uint32_t format, size_t plane, const struct i915_device* i915)
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{
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switch (format) {
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case DRM_FORMAT_NV12:
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case DRM_FORMAT_P010:
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case DRM_FORMAT_P016:
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return (i915->gen == 11 || i915->gen == 12) && plane == 1;
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}
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return false;
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}
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static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
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{
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uint32_t offset;
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size_t plane;
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int ret, pagesize;
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struct i915_device *i915 = bo->drv->priv;
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offset = 0;
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pagesize = getpagesize();
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for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
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uint32_t stride = drv_stride_from_format(format, width, plane);
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uint32_t plane_height = drv_height_from_format(format, height, plane);
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if (bo->meta.tiling != I915_TILING_NONE)
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assert(IS_ALIGNED(offset, pagesize));
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ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
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if (ret)
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return ret;
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if (i915_format_needs_LCU_alignment(format, plane, i915)) {
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/*
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* Align the height of the V plane for certain formats to the
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* largest coded unit (assuming that this BO may be used for video)
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* to be consistent with gmmlib.
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*/
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plane_height = ALIGN(plane_height, 64);
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}
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bo->meta.strides[plane] = stride;
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bo->meta.sizes[plane] = stride * plane_height;
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bo->meta.offsets[plane] = offset;
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offset += bo->meta.sizes[plane];
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}
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bo->meta.total_size = ALIGN(offset, pagesize);
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return 0;
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}
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static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
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uint64_t use_flags, const uint64_t *modifiers, uint32_t count)
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{
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uint64_t modifier;
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struct i915_device *i915 = bo->drv->priv;
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bool huge_bo = (i915->gen < 11) && (width > 4096);
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if (modifiers) {
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modifier =
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drv_pick_modifier(modifiers, count, i915->modifier.order, i915->modifier.count);
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} else {
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struct combination *combo = drv_get_combination(bo->drv, format, use_flags);
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if (!combo)
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return -EINVAL;
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modifier = combo->metadata.modifier;
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}
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/*
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* i915 only supports linear/x-tiled above 4096 wide on Gen9/Gen10 GPU.
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* VAAPI decode in NV12 Y tiled format so skip modifier change for NV12/P010 huge bo.
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*/
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if (huge_bo && format != DRM_FORMAT_NV12 && format != DRM_FORMAT_P010 &&
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modifier != I915_FORMAT_MOD_X_TILED && modifier != DRM_FORMAT_MOD_LINEAR) {
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uint32_t i;
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for (i = 0; modifiers && i < count; i++) {
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if (modifiers[i] == I915_FORMAT_MOD_X_TILED)
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break;
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}
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if (i == count)
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modifier = DRM_FORMAT_MOD_LINEAR;
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else
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modifier = I915_FORMAT_MOD_X_TILED;
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}
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/*
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* Skip I915_FORMAT_MOD_Y_TILED_CCS modifier if compression is disabled
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* Pick y tiled modifier if it has been passed in, otherwise use linear
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*/
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if (!bo->drv->compression && modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
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uint32_t i;
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for (i = 0; modifiers && i < count; i++) {
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if (modifiers[i] == I915_FORMAT_MOD_Y_TILED)
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break;
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}
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if (i == count)
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modifier = DRM_FORMAT_MOD_LINEAR;
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else
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modifier = I915_FORMAT_MOD_Y_TILED;
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}
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switch (modifier) {
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case DRM_FORMAT_MOD_LINEAR:
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bo->meta.tiling = I915_TILING_NONE;
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break;
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case I915_FORMAT_MOD_X_TILED:
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bo->meta.tiling = I915_TILING_X;
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break;
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case I915_FORMAT_MOD_Y_TILED:
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case I915_FORMAT_MOD_Y_TILED_CCS:
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bo->meta.tiling = I915_TILING_Y;
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break;
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}
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bo->meta.format_modifier = modifier;
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if (format == DRM_FORMAT_YVU420_ANDROID) {
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/*
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* We only need to be able to use this as a linear texture,
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* which doesn't put any HW restrictions on how we lay it
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* out. The Android format does require the stride to be a
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* multiple of 16 and expects the Cr and Cb stride to be
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* ALIGN(Y_stride / 2, 16), which we can make happen by
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* aligning to 32 bytes here.
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*/
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uint32_t stride = ALIGN(width, 32);
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drv_bo_from_format(bo, stride, height, format);
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} else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
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/*
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* For compressed surfaces, we need a color control surface
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|
* (CCS). Color compression is only supported for Y tiled
|
|
* surfaces, and for each 32x16 tiles in the main surface we
|
|
* need a tile in the control surface. Y tiles are 128 bytes
|
|
* wide and 32 lines tall and we use that to first compute the
|
|
* width and height in tiles of the main surface. stride and
|
|
* height are already multiples of 128 and 32, respectively:
|
|
*/
|
|
uint32_t stride = drv_stride_from_format(format, width, 0);
|
|
uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128);
|
|
uint32_t height_in_tiles = DIV_ROUND_UP(height, 32);
|
|
uint32_t size = width_in_tiles * height_in_tiles * 4096;
|
|
uint32_t offset = 0;
|
|
|
|
bo->meta.strides[0] = width_in_tiles * 128;
|
|
bo->meta.sizes[0] = size;
|
|
bo->meta.offsets[0] = offset;
|
|
offset += size;
|
|
|
|
/*
|
|
* Now, compute the width and height in tiles of the control
|
|
* surface by dividing and rounding up.
|
|
*/
|
|
uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
|
|
uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
|
|
uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
|
|
|
|
/*
|
|
* With stride and height aligned to y tiles, offset is
|
|
* already a multiple of 4096, which is the required alignment
|
|
* of the CCS.
|
|
*/
|
|
bo->meta.strides[1] = ccs_width_in_tiles * 128;
|
|
bo->meta.sizes[1] = ccs_size;
|
|
bo->meta.offsets[1] = offset;
|
|
offset += ccs_size;
|
|
|
|
bo->meta.num_planes = 2;
|
|
bo->meta.total_size = offset;
|
|
} else {
|
|
i915_bo_from_format(bo, width, height, format);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int i915_bo_create_from_metadata(struct bo *bo)
|
|
{
|
|
int ret;
|
|
size_t plane;
|
|
uint32_t gem_handle;
|
|
struct drm_i915_gem_set_tiling gem_set_tiling = { 0 };
|
|
struct i915_device *i915 = bo->drv->priv;
|
|
|
|
if (i915->has_hw_protection && (bo->meta.use_flags & BO_USE_PROTECTED)) {
|
|
struct drm_i915_gem_object_param protected_param = {
|
|
.param = I915_OBJECT_PARAM | I915_PARAM_PROTECTED_CONTENT,
|
|
.data = 1,
|
|
};
|
|
|
|
struct drm_i915_gem_create_ext_setparam setparam_protected = {
|
|
.base = { .name = I915_GEM_CREATE_EXT_SETPARAM },
|
|
.param = protected_param,
|
|
};
|
|
|
|
struct drm_i915_gem_create_ext create_ext = {
|
|
.size = bo->meta.total_size,
|
|
.extensions = (uintptr_t)&setparam_protected,
|
|
};
|
|
|
|
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
|
|
if (ret) {
|
|
drv_log("DRM_IOCTL_I915_GEM_CREATE_EXT failed (size=%llu)\n",
|
|
create_ext.size);
|
|
return -errno;
|
|
}
|
|
|
|
gem_handle = create_ext.handle;
|
|
} else {
|
|
struct drm_i915_gem_create gem_create = { 0 };
|
|
gem_create.size = bo->meta.total_size;
|
|
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
|
|
if (ret) {
|
|
drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
|
|
return -errno;
|
|
}
|
|
|
|
gem_handle = gem_create.handle;
|
|
}
|
|
|
|
for (plane = 0; plane < bo->meta.num_planes; plane++)
|
|
bo->handles[plane].u32 = gem_handle;
|
|
|
|
gem_set_tiling.handle = bo->handles[0].u32;
|
|
gem_set_tiling.tiling_mode = bo->meta.tiling;
|
|
gem_set_tiling.stride = bo->meta.strides[0];
|
|
|
|
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
|
|
if (ret) {
|
|
struct drm_gem_close gem_close = { 0 };
|
|
gem_close.handle = bo->handles[0].u32;
|
|
drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
|
|
|
|
drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
|
|
return -errno;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void i915_close(struct driver *drv)
|
|
{
|
|
free(drv->priv);
|
|
drv->priv = NULL;
|
|
}
|
|
|
|
static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
|
|
{
|
|
int ret;
|
|
struct drm_i915_gem_get_tiling gem_get_tiling = { 0 };
|
|
|
|
ret = drv_prime_bo_import(bo, data);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
|
|
gem_get_tiling.handle = bo->handles[0].u32;
|
|
|
|
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
|
|
if (ret) {
|
|
drv_gem_bo_destroy(bo);
|
|
drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
|
|
return ret;
|
|
}
|
|
|
|
bo->meta.tiling = gem_get_tiling.tiling_mode;
|
|
return 0;
|
|
}
|
|
|
|
static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
|
|
{
|
|
int ret;
|
|
void *addr = MAP_FAILED;
|
|
|
|
if (bo->meta.format_modifier == I915_FORMAT_MOD_Y_TILED_CCS)
|
|
return MAP_FAILED;
|
|
|
|
if (bo->meta.tiling == I915_TILING_NONE) {
|
|
struct drm_i915_gem_mmap gem_map = { 0 };
|
|
/* TODO(b/118799155): We don't seem to have a good way to
|
|
* detect the use cases for which WC mapping is really needed.
|
|
* The current heuristic seems overly coarse and may be slowing
|
|
* down some other use cases unnecessarily.
|
|
*
|
|
* For now, care must be taken not to use WC mappings for
|
|
* Renderscript and camera use cases, as they're
|
|
* performance-sensitive. */
|
|
if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
|
|
!(bo->meta.use_flags &
|
|
(BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
|
|
gem_map.flags = I915_MMAP_WC;
|
|
|
|
gem_map.handle = bo->handles[0].u32;
|
|
gem_map.offset = 0;
|
|
gem_map.size = bo->meta.total_size;
|
|
|
|
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
|
|
/* DRM_IOCTL_I915_GEM_MMAP mmaps the underlying shm
|
|
* file and returns a user space address directly, ie,
|
|
* doesn't go through mmap. If we try that on a
|
|
* dma-buf that doesn't have a shm file, i915.ko
|
|
* returns ENXIO. Fall through to
|
|
* DRM_IOCTL_I915_GEM_MMAP_GTT in that case, which
|
|
* will mmap on the drm fd instead. */
|
|
if (ret == 0)
|
|
addr = (void *)(uintptr_t)gem_map.addr_ptr;
|
|
}
|
|
|
|
if (addr == MAP_FAILED) {
|
|
struct drm_i915_gem_mmap_gtt gem_map = { 0 };
|
|
|
|
gem_map.handle = bo->handles[0].u32;
|
|
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
|
|
if (ret) {
|
|
drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
|
|
return MAP_FAILED;
|
|
}
|
|
|
|
addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
|
|
bo->drv->fd, gem_map.offset);
|
|
}
|
|
|
|
if (addr == MAP_FAILED) {
|
|
drv_log("i915 GEM mmap failed\n");
|
|
return addr;
|
|
}
|
|
|
|
vma->length = bo->meta.total_size;
|
|
return addr;
|
|
}
|
|
|
|
static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
|
|
{
|
|
int ret;
|
|
struct drm_i915_gem_set_domain set_domain = { 0 };
|
|
|
|
set_domain.handle = bo->handles[0].u32;
|
|
if (bo->meta.tiling == I915_TILING_NONE) {
|
|
set_domain.read_domains = I915_GEM_DOMAIN_CPU;
|
|
if (mapping->vma->map_flags & BO_MAP_WRITE)
|
|
set_domain.write_domain = I915_GEM_DOMAIN_CPU;
|
|
} else {
|
|
set_domain.read_domains = I915_GEM_DOMAIN_GTT;
|
|
if (mapping->vma->map_flags & BO_MAP_WRITE)
|
|
set_domain.write_domain = I915_GEM_DOMAIN_GTT;
|
|
}
|
|
|
|
ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
|
|
if (ret) {
|
|
drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
|
|
{
|
|
struct i915_device *i915 = bo->drv->priv;
|
|
if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
|
|
i915_clflush(mapping->vma->addr, mapping->vma->length);
|
|
|
|
return 0;
|
|
}
|
|
|
|
const struct backend backend_i915 = {
|
|
.name = "i915",
|
|
.init = i915_init,
|
|
.close = i915_close,
|
|
.bo_compute_metadata = i915_bo_compute_metadata,
|
|
.bo_create_from_metadata = i915_bo_create_from_metadata,
|
|
.bo_destroy = drv_gem_bo_destroy,
|
|
.bo_import = i915_bo_import,
|
|
.bo_map = i915_bo_map,
|
|
.bo_unmap = drv_bo_munmap,
|
|
.bo_invalidate = i915_bo_invalidate,
|
|
.bo_flush = i915_bo_flush,
|
|
.resolve_format = drv_resolve_format_helper,
|
|
};
|
|
|
|
#endif
|