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226 lines
7.7 KiB
226 lines
7.7 KiB
/*
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* Copyright (C) 2016 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_OPTIMIZING_COMMON_ARM_H_
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#define ART_COMPILER_OPTIMIZING_COMMON_ARM_H_
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#include "instruction_simplifier_shared.h"
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#include "locations.h"
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#include "nodes.h"
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#include "utils/arm/constants_arm.h"
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// TODO(VIXL): Make VIXL compile with -Wshadow.
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wshadow"
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#include "aarch32/macro-assembler-aarch32.h"
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#pragma GCC diagnostic pop
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namespace art {
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using helpers::HasShifterOperand;
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namespace arm {
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namespace helpers {
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static_assert(vixl::aarch32::kSpCode == SP, "vixl::aarch32::kSpCode must equal ART's SP");
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inline vixl::aarch32::Register HighRegisterFrom(Location location) {
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DCHECK(location.IsRegisterPair()) << location;
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return vixl::aarch32::Register(location.AsRegisterPairHigh<vixl::aarch32::Register>());
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}
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inline vixl::aarch32::DRegister HighDRegisterFrom(Location location) {
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DCHECK(location.IsFpuRegisterPair()) << location;
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return vixl::aarch32::DRegister(location.AsFpuRegisterPairHigh<vixl::aarch32::DRegister>());
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}
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inline vixl::aarch32::Register LowRegisterFrom(Location location) {
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DCHECK(location.IsRegisterPair()) << location;
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return vixl::aarch32::Register(location.AsRegisterPairLow<vixl::aarch32::Register>());
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}
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inline vixl::aarch32::SRegister LowSRegisterFrom(Location location) {
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DCHECK(location.IsFpuRegisterPair()) << location;
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return vixl::aarch32::SRegister(location.AsFpuRegisterPairLow<vixl::aarch32::SRegister>());
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}
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inline vixl::aarch32::SRegister HighSRegisterFrom(Location location) {
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DCHECK(location.IsFpuRegisterPair()) << location;
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return vixl::aarch32::SRegister(location.AsFpuRegisterPairHigh<vixl::aarch32::SRegister>());
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}
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inline vixl::aarch32::Register RegisterFrom(Location location) {
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DCHECK(location.IsRegister()) << location;
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return vixl::aarch32::Register(location.reg());
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}
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inline vixl::aarch32::Register RegisterFrom(Location location, DataType::Type type) {
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DCHECK(type != DataType::Type::kVoid && !DataType::IsFloatingPointType(type)) << type;
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return RegisterFrom(location);
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}
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inline vixl::aarch32::DRegister DRegisterFrom(Location location) {
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DCHECK(location.IsFpuRegisterPair()) << location;
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int reg_code = location.low();
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DCHECK_EQ(reg_code % 2, 0) << reg_code;
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return vixl::aarch32::DRegister(reg_code / 2);
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}
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inline vixl::aarch32::SRegister SRegisterFrom(Location location) {
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DCHECK(location.IsFpuRegister()) << location;
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return vixl::aarch32::SRegister(location.reg());
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}
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inline vixl::aarch32::SRegister OutputSRegister(HInstruction* instr) {
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DataType::Type type = instr->GetType();
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DCHECK_EQ(type, DataType::Type::kFloat32) << type;
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return SRegisterFrom(instr->GetLocations()->Out());
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}
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inline vixl::aarch32::DRegister OutputDRegister(HInstruction* instr) {
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DataType::Type type = instr->GetType();
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DCHECK_EQ(type, DataType::Type::kFloat64) << type;
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return DRegisterFrom(instr->GetLocations()->Out());
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}
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inline vixl::aarch32::VRegister OutputVRegister(HInstruction* instr) {
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DataType::Type type = instr->GetType();
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if (type == DataType::Type::kFloat32) {
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return OutputSRegister(instr);
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} else {
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return OutputDRegister(instr);
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}
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}
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inline vixl::aarch32::SRegister InputSRegisterAt(HInstruction* instr, int input_index) {
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DataType::Type type = instr->InputAt(input_index)->GetType();
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DCHECK_EQ(type, DataType::Type::kFloat32) << type;
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return SRegisterFrom(instr->GetLocations()->InAt(input_index));
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}
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inline vixl::aarch32::DRegister InputDRegisterAt(HInstruction* instr, int input_index) {
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DataType::Type type = instr->InputAt(input_index)->GetType();
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DCHECK_EQ(type, DataType::Type::kFloat64) << type;
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return DRegisterFrom(instr->GetLocations()->InAt(input_index));
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}
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inline vixl::aarch32::VRegister InputVRegisterAt(HInstruction* instr, int input_index) {
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DataType::Type type = instr->InputAt(input_index)->GetType();
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if (type == DataType::Type::kFloat32) {
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return InputSRegisterAt(instr, input_index);
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} else {
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DCHECK_EQ(type, DataType::Type::kFloat64);
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return InputDRegisterAt(instr, input_index);
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}
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}
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inline vixl::aarch32::VRegister InputVRegister(HInstruction* instr) {
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DCHECK_EQ(instr->InputCount(), 1u);
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return InputVRegisterAt(instr, 0);
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}
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inline vixl::aarch32::Register OutputRegister(HInstruction* instr) {
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return RegisterFrom(instr->GetLocations()->Out(), instr->GetType());
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}
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inline vixl::aarch32::Register InputRegisterAt(HInstruction* instr, int input_index) {
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return RegisterFrom(instr->GetLocations()->InAt(input_index),
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instr->InputAt(input_index)->GetType());
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}
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inline vixl::aarch32::Register InputRegister(HInstruction* instr) {
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DCHECK_EQ(instr->InputCount(), 1u);
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return InputRegisterAt(instr, 0);
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}
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inline vixl::aarch32::DRegister DRegisterFromS(vixl::aarch32::SRegister s) {
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vixl::aarch32::DRegister d = vixl::aarch32::DRegister(s.GetCode() / 2);
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DCHECK(s.Is(d.GetLane(0)) || s.Is(d.GetLane(1)));
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return d;
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}
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inline int32_t Int32ConstantFrom(HInstruction* instr) {
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if (instr->IsIntConstant()) {
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return instr->AsIntConstant()->GetValue();
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} else if (instr->IsNullConstant()) {
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return 0;
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} else {
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DCHECK(instr->IsLongConstant()) << instr->DebugName();
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const int64_t ret = instr->AsLongConstant()->GetValue();
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DCHECK_GE(ret, std::numeric_limits<int32_t>::min());
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DCHECK_LE(ret, std::numeric_limits<int32_t>::max());
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return ret;
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}
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}
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inline int32_t Int32ConstantFrom(Location location) {
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return Int32ConstantFrom(location.GetConstant());
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}
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inline int64_t Int64ConstantFrom(Location location) {
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HConstant* instr = location.GetConstant();
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if (instr->IsIntConstant()) {
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return instr->AsIntConstant()->GetValue();
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} else if (instr->IsNullConstant()) {
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return 0;
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} else {
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DCHECK(instr->IsLongConstant()) << instr->DebugName();
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return instr->AsLongConstant()->GetValue();
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}
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}
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inline uint64_t Uint64ConstantFrom(HInstruction* instr) {
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DCHECK(instr->IsConstant()) << instr->DebugName();
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return instr->AsConstant()->GetValueAsUint64();
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}
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inline vixl::aarch32::Operand OperandFrom(Location location, DataType::Type type) {
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if (location.IsRegister()) {
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return vixl::aarch32::Operand(RegisterFrom(location, type));
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} else {
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return vixl::aarch32::Operand(Int32ConstantFrom(location));
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}
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}
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inline vixl::aarch32::Operand InputOperandAt(HInstruction* instr, int input_index) {
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return OperandFrom(instr->GetLocations()->InAt(input_index),
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instr->InputAt(input_index)->GetType());
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}
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inline Location LocationFrom(const vixl::aarch32::Register& reg) {
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return Location::RegisterLocation(reg.GetCode());
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}
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inline Location LocationFrom(const vixl::aarch32::SRegister& reg) {
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return Location::FpuRegisterLocation(reg.GetCode());
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}
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inline Location LocationFrom(const vixl::aarch32::Register& low,
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const vixl::aarch32::Register& high) {
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return Location::RegisterPairLocation(low.GetCode(), high.GetCode());
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}
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inline Location LocationFrom(const vixl::aarch32::SRegister& low,
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const vixl::aarch32::SRegister& high) {
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return Location::FpuRegisterPairLocation(low.GetCode(), high.GetCode());
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}
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} // namespace helpers
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} // namespace arm
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} // namespace art
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#endif // ART_COMPILER_OPTIMIZING_COMMON_ARM_H_
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