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82 lines
2.9 KiB
82 lines
2.9 KiB
/*
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* Copyright (C) 2015 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_OPTIMIZING_INSTRUCTION_SIMPLIFIER_SHARED_H_
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#define ART_COMPILER_OPTIMIZING_INSTRUCTION_SIMPLIFIER_SHARED_H_
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#include "nodes.h"
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namespace art {
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namespace helpers {
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inline bool CanFitInShifterOperand(HInstruction* instruction) {
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if (instruction->IsTypeConversion()) {
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HTypeConversion* conversion = instruction->AsTypeConversion();
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DataType::Type result_type = conversion->GetResultType();
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DataType::Type input_type = conversion->GetInputType();
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// We don't expect to see the same type as input and result.
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return DataType::IsIntegralType(result_type) && DataType::IsIntegralType(input_type) &&
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(result_type != input_type);
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} else {
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return (instruction->IsShl() && instruction->AsShl()->InputAt(1)->IsIntConstant()) ||
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(instruction->IsShr() && instruction->AsShr()->InputAt(1)->IsIntConstant()) ||
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(instruction->IsUShr() && instruction->AsUShr()->InputAt(1)->IsIntConstant());
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}
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}
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inline bool HasShifterOperand(HInstruction* instr, InstructionSet isa) {
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// On ARM64 `neg` instructions are an alias of `sub` using the zero register
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// as the first register input.
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bool res = instr->IsAdd() || instr->IsAnd() ||
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(isa == InstructionSet::kArm64 && instr->IsNeg()) ||
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instr->IsOr() || instr->IsSub() || instr->IsXor();
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return res;
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}
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// Check the specified sub is the last operation of the sequence:
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// t1 = Shl
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// t2 = Sub(t1, *)
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// t3 = Sub(*, t2)
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inline bool IsSubRightSubLeftShl(HSub *sub) {
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HInstruction* right = sub->GetRight();
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return right->IsSub() && right->AsSub()->GetLeft()->IsShl();;
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}
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} // namespace helpers
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bool TryCombineMultiplyAccumulate(HMul* mul, InstructionSet isa);
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// For bitwise operations (And/Or/Xor) with a negated input, try to use
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// a negated bitwise instruction.
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bool TryMergeNegatedInput(HBinaryOperation* op);
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bool TryExtractArrayAccessAddress(HInstruction* access,
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HInstruction* array,
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HInstruction* index,
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size_t data_offset);
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bool TryExtractVecArrayAccessAddress(HVecMemoryOperation* access, HInstruction* index);
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// Try to replace
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// Sub(c, Sub(a, b))
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// with
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// Add(c, Sub(b, a))
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bool TryReplaceSubSubWithSubAdd(HSub* last_sub);
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} // namespace art
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#endif // ART_COMPILER_OPTIMIZING_INSTRUCTION_SIMPLIFIER_SHARED_H_
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