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180 lines
7.6 KiB
180 lines
7.6 KiB
/*
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* Copyright (C) 2016 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_OPTIMIZING_SCHEDULER_ARM64_H_
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#define ART_COMPILER_OPTIMIZING_SCHEDULER_ARM64_H_
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#include "scheduler.h"
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namespace art {
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namespace arm64 {
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static constexpr uint32_t kArm64MemoryLoadLatency = 5;
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static constexpr uint32_t kArm64MemoryStoreLatency = 3;
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static constexpr uint32_t kArm64CallInternalLatency = 10;
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static constexpr uint32_t kArm64CallLatency = 5;
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// AArch64 instruction latency.
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// We currently assume that all arm64 CPUs share the same instruction latency list.
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static constexpr uint32_t kArm64IntegerOpLatency = 2;
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static constexpr uint32_t kArm64FloatingPointOpLatency = 5;
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static constexpr uint32_t kArm64DataProcWithShifterOpLatency = 3;
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static constexpr uint32_t kArm64DivDoubleLatency = 30;
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static constexpr uint32_t kArm64DivFloatLatency = 15;
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static constexpr uint32_t kArm64DivIntegerLatency = 5;
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static constexpr uint32_t kArm64LoadStringInternalLatency = 7;
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static constexpr uint32_t kArm64MulFloatingPointLatency = 6;
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static constexpr uint32_t kArm64MulIntegerLatency = 6;
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static constexpr uint32_t kArm64TypeConversionFloatingPointIntegerLatency = 5;
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static constexpr uint32_t kArm64BranchLatency = kArm64IntegerOpLatency;
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static constexpr uint32_t kArm64SIMDFloatingPointOpLatency = 10;
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static constexpr uint32_t kArm64SIMDIntegerOpLatency = 6;
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static constexpr uint32_t kArm64SIMDMemoryLoadLatency = 10;
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static constexpr uint32_t kArm64SIMDMemoryStoreLatency = 6;
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static constexpr uint32_t kArm64SIMDMulFloatingPointLatency = 12;
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static constexpr uint32_t kArm64SIMDMulIntegerLatency = 12;
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static constexpr uint32_t kArm64SIMDReplicateOpLatency = 16;
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static constexpr uint32_t kArm64SIMDDivDoubleLatency = 60;
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static constexpr uint32_t kArm64SIMDDivFloatLatency = 30;
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static constexpr uint32_t kArm64SIMDTypeConversionInt2FPLatency = 10;
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class SchedulingLatencyVisitorARM64 : public SchedulingLatencyVisitor {
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public:
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// Default visitor for instructions not handled specifically below.
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void VisitInstruction(HInstruction* ATTRIBUTE_UNUSED) override {
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last_visited_latency_ = kArm64IntegerOpLatency;
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}
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// We add a second unused parameter to be able to use this macro like the others
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// defined in `nodes.h`.
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#define FOR_EACH_SCHEDULED_COMMON_INSTRUCTION(M) \
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M(ArrayGet , unused) \
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M(ArrayLength , unused) \
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M(ArraySet , unused) \
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M(BoundsCheck , unused) \
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M(Div , unused) \
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M(InstanceFieldGet , unused) \
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M(InstanceOf , unused) \
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M(LoadString , unused) \
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M(Mul , unused) \
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M(NewArray , unused) \
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M(NewInstance , unused) \
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M(Rem , unused) \
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M(StaticFieldGet , unused) \
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M(SuspendCheck , unused) \
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M(TypeConversion , unused) \
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M(VecReplicateScalar , unused) \
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M(VecExtractScalar , unused) \
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M(VecReduce , unused) \
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M(VecCnv , unused) \
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M(VecNeg , unused) \
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M(VecAbs , unused) \
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M(VecNot , unused) \
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M(VecAdd , unused) \
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M(VecHalvingAdd , unused) \
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M(VecSub , unused) \
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M(VecMul , unused) \
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M(VecDiv , unused) \
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M(VecMin , unused) \
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M(VecMax , unused) \
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M(VecAnd , unused) \
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M(VecAndNot , unused) \
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M(VecOr , unused) \
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M(VecXor , unused) \
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M(VecShl , unused) \
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M(VecShr , unused) \
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M(VecUShr , unused) \
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M(VecSetScalars , unused) \
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M(VecMultiplyAccumulate, unused) \
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M(VecLoad , unused) \
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M(VecStore , unused)
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#define FOR_EACH_SCHEDULED_ABSTRACT_INSTRUCTION(M) \
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M(BinaryOperation , unused) \
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M(Invoke , unused)
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#define FOR_EACH_SCHEDULED_SHARED_INSTRUCTION(M) \
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M(BitwiseNegatedRight, unused) \
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M(MultiplyAccumulate, unused) \
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M(IntermediateAddress, unused) \
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M(IntermediateAddressIndex, unused) \
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M(DataProcWithShifterOp, unused)
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#define DECLARE_VISIT_INSTRUCTION(type, unused) \
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void Visit##type(H##type* instruction) override;
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FOR_EACH_SCHEDULED_COMMON_INSTRUCTION(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_SCHEDULED_ABSTRACT_INSTRUCTION(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_SCHEDULED_SHARED_INSTRUCTION(DECLARE_VISIT_INSTRUCTION)
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FOR_EACH_CONCRETE_INSTRUCTION_ARM64(DECLARE_VISIT_INSTRUCTION)
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#undef DECLARE_VISIT_INSTRUCTION
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private:
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void HandleSimpleArithmeticSIMD(HVecOperation *instr);
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void HandleVecAddress(HVecMemoryOperation* instruction, size_t size);
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};
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class HSchedulerARM64 : public HScheduler {
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public:
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explicit HSchedulerARM64(SchedulingNodeSelector* selector)
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: HScheduler(&arm64_latency_visitor_, selector) {}
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~HSchedulerARM64() override {}
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bool IsSchedulable(const HInstruction* instruction) const override {
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#define CASE_INSTRUCTION_KIND(type, unused) case \
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HInstruction::InstructionKind::k##type:
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switch (instruction->GetKind()) {
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FOR_EACH_SCHEDULED_SHARED_INSTRUCTION(CASE_INSTRUCTION_KIND)
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return true;
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FOR_EACH_CONCRETE_INSTRUCTION_ARM64(CASE_INSTRUCTION_KIND)
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return true;
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FOR_EACH_SCHEDULED_COMMON_INSTRUCTION(CASE_INSTRUCTION_KIND)
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return true;
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default:
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return HScheduler::IsSchedulable(instruction);
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}
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#undef CASE_INSTRUCTION_KIND
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}
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// Treat as scheduling barriers those vector instructions whose live ranges exceed the vectorized
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// loop boundaries. This is a workaround for the lack of notion of SIMD register in the compiler;
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// around a call we have to save/restore all live SIMD&FP registers (only lower 64 bits of
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// SIMD&FP registers are callee saved) so don't reorder such vector instructions.
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//
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// TODO: remove this when a proper support of SIMD registers is introduced to the compiler.
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bool IsSchedulingBarrier(const HInstruction* instr) const override {
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return HScheduler::IsSchedulingBarrier(instr) ||
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instr->IsVecReduce() ||
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instr->IsVecExtractScalar() ||
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instr->IsVecSetScalars() ||
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instr->IsVecReplicateScalar();
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}
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private:
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SchedulingLatencyVisitorARM64 arm64_latency_visitor_;
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DISALLOW_COPY_AND_ASSIGN(HSchedulerARM64);
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};
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} // namespace arm64
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} // namespace art
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#endif // ART_COMPILER_OPTIMIZING_SCHEDULER_ARM64_H_
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