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281 lines
11 KiB
281 lines
11 KiB
/*
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* Copyright (C) 2016 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM_VIXL_H_
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#define ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM_VIXL_H_
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#include <android-base/logging.h>
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#include "base/arena_containers.h"
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#include "base/macros.h"
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#include "constants_arm.h"
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#include "dwarf/register.h"
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#include "offsets.h"
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#include "utils/arm/assembler_arm_shared.h"
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#include "utils/arm/managed_register_arm.h"
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#include "utils/assembler.h"
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#include "utils/jni_macro_assembler.h"
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// TODO(VIXL): Make VIXL compile with -Wshadow and remove pragmas.
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wshadow"
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#include "aarch32/macro-assembler-aarch32.h"
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#pragma GCC diagnostic pop
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namespace vixl32 = vixl::aarch32;
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namespace art {
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namespace arm {
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inline dwarf::Reg DWARFReg(vixl32::Register reg) {
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return dwarf::Reg::ArmCore(static_cast<int>(reg.GetCode()));
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}
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inline dwarf::Reg DWARFReg(vixl32::SRegister reg) {
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return dwarf::Reg::ArmFp(static_cast<int>(reg.GetCode()));
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}
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class ArmVIXLMacroAssembler final : public vixl32::MacroAssembler {
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public:
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// Most methods fit in a 1KB code buffer, which results in more optimal alloc/realloc and
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// fewer system calls than a larger default capacity.
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static constexpr size_t kDefaultCodeBufferCapacity = 1 * KB;
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ArmVIXLMacroAssembler()
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: vixl32::MacroAssembler(ArmVIXLMacroAssembler::kDefaultCodeBufferCapacity) {}
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// The following interfaces can generate CMP+Bcc or Cbz/Cbnz.
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// CMP+Bcc are generated by default.
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// If a hint is given (is_far_target = false) and rn and label can all fit into Cbz/Cbnz,
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// then Cbz/Cbnz is generated.
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// Prefer following interfaces to using vixl32::MacroAssembler::Cbz/Cbnz.
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// In T32, Cbz/Cbnz instructions have following limitations:
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// - Far targets, which are over 126 bytes away, are not supported.
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// - Only low registers can be encoded.
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// - Backward branches are not supported.
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void CompareAndBranchIfZero(vixl32::Register rn,
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vixl32::Label* label,
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bool is_far_target = true);
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void CompareAndBranchIfNonZero(vixl32::Register rn,
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vixl32::Label* label,
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bool is_far_target = true);
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// In T32 some of the instructions (add, mov, etc) outside an IT block
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// have only 32-bit encodings. But there are 16-bit flag setting
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// versions of these instructions (adds, movs, etc). In most of the
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// cases in ART we don't care if the instructions keep flags or not;
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// thus we can benefit from smaller code size.
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// VIXL will never generate flag setting versions (for example, adds
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// for Add macro instruction) unless vixl32::DontCare option is
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// explicitly specified. That's why we introduce wrappers to use
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// DontCare option by default.
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#define WITH_FLAGS_DONT_CARE_RD_RN_OP(func_name) \
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void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
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MacroAssembler::func_name(vixl32::DontCare, rd, rn, operand); \
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} \
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using MacroAssembler::func_name
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WITH_FLAGS_DONT_CARE_RD_RN_OP(Adc);
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WITH_FLAGS_DONT_CARE_RD_RN_OP(Sub);
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WITH_FLAGS_DONT_CARE_RD_RN_OP(Sbc);
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WITH_FLAGS_DONT_CARE_RD_RN_OP(Rsb);
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WITH_FLAGS_DONT_CARE_RD_RN_OP(Rsc);
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WITH_FLAGS_DONT_CARE_RD_RN_OP(Eor);
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WITH_FLAGS_DONT_CARE_RD_RN_OP(Orr);
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WITH_FLAGS_DONT_CARE_RD_RN_OP(Orn);
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WITH_FLAGS_DONT_CARE_RD_RN_OP(And);
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WITH_FLAGS_DONT_CARE_RD_RN_OP(Bic);
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WITH_FLAGS_DONT_CARE_RD_RN_OP(Asr);
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WITH_FLAGS_DONT_CARE_RD_RN_OP(Lsr);
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WITH_FLAGS_DONT_CARE_RD_RN_OP(Lsl);
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WITH_FLAGS_DONT_CARE_RD_RN_OP(Ror);
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#undef WITH_FLAGS_DONT_CARE_RD_RN_OP
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#define WITH_FLAGS_DONT_CARE_RD_OP(func_name) \
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void (func_name)(vixl32::Register rd, const vixl32::Operand& operand) { \
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MacroAssembler::func_name(vixl32::DontCare, rd, operand); \
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} \
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using MacroAssembler::func_name
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WITH_FLAGS_DONT_CARE_RD_OP(Mvn);
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WITH_FLAGS_DONT_CARE_RD_OP(Mov);
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#undef WITH_FLAGS_DONT_CARE_RD_OP
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// The following two functions don't fall into above categories. Overload them separately.
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void Rrx(vixl32::Register rd, vixl32::Register rn) {
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MacroAssembler::Rrx(vixl32::DontCare, rd, rn);
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}
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using MacroAssembler::Rrx;
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void Mul(vixl32::Register rd, vixl32::Register rn, vixl32::Register rm) {
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MacroAssembler::Mul(vixl32::DontCare, rd, rn, rm);
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}
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using MacroAssembler::Mul;
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// TODO: Remove when MacroAssembler::Add(FlagsUpdate, Condition, Register, Register, Operand)
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// makes the right decision about 16-bit encodings.
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void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) {
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if (rd.Is(rn) && operand.IsPlainRegister()) {
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MacroAssembler::Add(rd, rn, operand);
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} else {
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MacroAssembler::Add(vixl32::DontCare, rd, rn, operand);
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}
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}
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using MacroAssembler::Add;
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// These interfaces try to use 16-bit T2 encoding of B instruction.
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void B(vixl32::Label* label);
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// For B(label), we always try to use Narrow encoding, because 16-bit T2 encoding supports
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// jumping within 2KB range. For B(cond, label), because the supported branch range is 256
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// bytes; we use the far_target hint to try to use 16-bit T1 encoding for short range jumps.
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void B(vixl32::Condition cond, vixl32::Label* label, bool is_far_target = true);
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// Use literal for generating double constant if it doesn't fit VMOV encoding.
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void Vmov(vixl32::DRegister rd, double imm) {
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if (vixl::VFP::IsImmFP64(imm)) {
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MacroAssembler::Vmov(rd, imm);
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} else {
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MacroAssembler::Vldr(rd, imm);
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}
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}
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using MacroAssembler::Vmov;
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};
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class ArmVIXLAssembler final : public Assembler {
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private:
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class ArmException;
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public:
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explicit ArmVIXLAssembler(ArenaAllocator* allocator)
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: Assembler(allocator) {
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// Use Thumb2 instruction set.
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vixl_masm_.UseT32();
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}
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virtual ~ArmVIXLAssembler() {}
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ArmVIXLMacroAssembler* GetVIXLAssembler() { return &vixl_masm_; }
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void FinalizeCode() override;
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// Size of generated code.
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size_t CodeSize() const override;
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const uint8_t* CodeBufferBaseAddress() const override;
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// Copy instructions out of assembly buffer into the given region of memory.
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void FinalizeInstructions(const MemoryRegion& region) override;
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void Bind(Label* label ATTRIBUTE_UNUSED) override {
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UNIMPLEMENTED(FATAL) << "Do not use Bind(Label*) for ARM";
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}
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void Jump(Label* label ATTRIBUTE_UNUSED) override {
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UNIMPLEMENTED(FATAL) << "Do not use Jump(Label*) for ARM";
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}
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void Bind(vixl::aarch32::Label* label) {
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vixl_masm_.Bind(label);
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}
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void Jump(vixl::aarch32::Label* label) {
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vixl_masm_.B(label);
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}
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//
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// Heap poisoning.
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//
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// Poison a heap reference contained in `reg`.
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void PoisonHeapReference(vixl32::Register reg);
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// Unpoison a heap reference contained in `reg`.
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void UnpoisonHeapReference(vixl32::Register reg);
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// Poison a heap reference contained in `reg` if heap poisoning is enabled.
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void MaybePoisonHeapReference(vixl32::Register reg);
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// Unpoison a heap reference contained in `reg` if heap poisoning is enabled.
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void MaybeUnpoisonHeapReference(vixl32::Register reg);
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// Emit code checking the status of the Marking Register, and aborting
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// the program if MR does not match the value stored in the art::Thread
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// object.
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//
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// Argument `temp` is used as a temporary register to generate code.
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// Argument `code` is used to identify the different occurrences of
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// MaybeGenerateMarkingRegisterCheck and is passed to the BKPT instruction.
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void GenerateMarkingRegisterCheck(vixl32::Register temp, int code = 0);
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void StoreToOffset(StoreOperandType type,
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vixl32::Register reg,
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vixl32::Register base,
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int32_t offset);
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void StoreSToOffset(vixl32::SRegister source, vixl32::Register base, int32_t offset);
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void StoreDToOffset(vixl32::DRegister source, vixl32::Register base, int32_t offset);
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void LoadImmediate(vixl32::Register dest, int32_t value);
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void LoadFromOffset(LoadOperandType type,
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vixl32::Register reg,
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vixl32::Register base,
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int32_t offset);
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void LoadSFromOffset(vixl32::SRegister reg, vixl32::Register base, int32_t offset);
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void LoadDFromOffset(vixl32::DRegister reg, vixl32::Register base, int32_t offset);
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void LoadRegisterList(RegList regs, size_t stack_offset);
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void StoreRegisterList(RegList regs, size_t stack_offset);
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bool ShifterOperandCanAlwaysHold(uint32_t immediate);
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bool ShifterOperandCanHold(Opcode opcode,
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uint32_t immediate,
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vixl::aarch32::FlagsUpdate update_flags = vixl::aarch32::DontCare);
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bool CanSplitLoadStoreOffset(int32_t allowed_offset_bits,
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int32_t offset,
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/*out*/ int32_t* add_to_base,
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/*out*/ int32_t* offset_for_load_store);
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int32_t AdjustLoadStoreOffset(int32_t allowed_offset_bits,
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vixl32::Register temp,
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vixl32::Register base,
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int32_t offset);
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int32_t GetAllowedLoadOffsetBits(LoadOperandType type);
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int32_t GetAllowedStoreOffsetBits(StoreOperandType type);
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void AddConstant(vixl32::Register rd, int32_t value);
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void AddConstant(vixl32::Register rd, vixl32::Register rn, int32_t value);
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void AddConstantInIt(vixl32::Register rd,
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vixl32::Register rn,
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int32_t value,
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vixl32::Condition cond = vixl32::al);
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template <typename T>
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vixl::aarch32::Literal<T>* CreateLiteralDestroyedWithPool(T value) {
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vixl::aarch32::Literal<T>* literal =
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new vixl::aarch32::Literal<T>(value,
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vixl32::RawLiteral::kPlacedWhenUsed,
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vixl32::RawLiteral::kDeletedOnPoolDestruction);
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return literal;
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}
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private:
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// VIXL assembler.
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ArmVIXLMacroAssembler vixl_masm_;
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};
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// Thread register declaration.
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extern const vixl32::Register tr;
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// Marking register declaration.
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extern const vixl32::Register mr;
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} // namespace arm
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} // namespace art
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#endif // ART_COMPILER_UTILS_ARM_ASSEMBLER_ARM_VIXL_H_
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