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136 lines
3.1 KiB
136 lines
3.1 KiB
/*
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* Copyright (C) 2009 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_
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#define ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_
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#include <stdint.h>
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#include <iosfwd>
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#include <android-base/logging.h>
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#include "arch/arm/registers_arm.h"
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#include "base/casts.h"
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#include "base/globals.h"
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namespace art {
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namespace arm {
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// Defines constants and accessor classes to assemble, disassemble and
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// simulate ARM instructions.
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//
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// Section references in the code refer to the "ARM Architecture
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// Reference Manual ARMv7-A and ARMv7-R edition", issue C.b (24 July
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// 2012).
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//
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// Constants for specific fields are defined in their respective named enums.
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// General constants are in an anonymous enum in class Instr.
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// 4 bits option for the dmb instruction.
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// Order and values follows those of the ARM Architecture Reference Manual.
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enum DmbOptions {
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SY = 0xf,
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ST = 0xe,
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ISH = 0xb,
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ISHST = 0xa,
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NSH = 0x7,
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NSHST = 0x6
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};
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enum ScaleFactor {
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TIMES_1 = 0,
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TIMES_2 = 1,
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TIMES_4 = 2,
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TIMES_8 = 3
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};
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// Values for double-precision floating point registers.
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enum DRegister { // private marker to avoid generate-operator-out.py from processing.
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D0 = 0,
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D1 = 1,
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D2 = 2,
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D3 = 3,
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D4 = 4,
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D5 = 5,
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D6 = 6,
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D7 = 7,
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D8 = 8,
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D9 = 9,
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D10 = 10,
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D11 = 11,
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D12 = 12,
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D13 = 13,
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D14 = 14,
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D15 = 15,
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D16 = 16,
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D17 = 17,
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D18 = 18,
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D19 = 19,
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D20 = 20,
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D21 = 21,
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D22 = 22,
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D23 = 23,
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D24 = 24,
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D25 = 25,
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D26 = 26,
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D27 = 27,
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D28 = 28,
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D29 = 29,
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D30 = 30,
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D31 = 31,
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kNumberOfDRegisters = 32,
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kNumberOfOverlappingDRegisters = 16,
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kNoDRegister = -1,
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};
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std::ostream& operator<<(std::ostream& os, const DRegister& rhs);
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// Opcodes for Data-processing instructions (instructions with a type 0 and 1)
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// as defined in section A3.4
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enum Opcode {
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kNoOperand = -1,
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AND = 0, // Logical AND
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EOR = 1, // Logical Exclusive OR
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SUB = 2, // Subtract
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RSB = 3, // Reverse Subtract
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ADD = 4, // Add
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ADC = 5, // Add with Carry
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SBC = 6, // Subtract with Carry
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RSC = 7, // Reverse Subtract with Carry
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TST = 8, // Test
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TEQ = 9, // Test Equivalence
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CMP = 10, // Compare
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CMN = 11, // Compare Negated
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ORR = 12, // Logical (inclusive) OR
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MOV = 13, // Move
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BIC = 14, // Bit Clear
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MVN = 15, // Move Not
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ORN = 16, // Logical OR NOT.
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kMaxOperand = 17
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};
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// Size (in bytes) of registers.
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const int kRegisterSize = 4;
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// List of registers used in load/store multiple.
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typedef uint16_t RegList;
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} // namespace arm
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} // namespace art
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#endif // ART_COMPILER_UTILS_ARM_CONSTANTS_ARM_H_
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