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211 lines
7.2 KiB
211 lines
7.2 KiB
/*
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* Copyright (C) 2014 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "arch/arm64/instruction_set_features_arm64.h"
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#include "assembler_arm64.h"
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#include "base/bit_utils_iterator.h"
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#include "entrypoints/quick/quick_entrypoints.h"
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#include "heap_poisoning.h"
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#include "offsets.h"
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#include "thread.h"
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using namespace vixl::aarch64; // NOLINT(build/namespaces)
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namespace art {
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namespace arm64 {
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#ifdef ___
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#error "ARM64 Assembler macro already defined."
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#else
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#define ___ vixl_masm_.
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#endif
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// Sets vixl::CPUFeatures according to ART instruction set features.
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static void SetVIXLCPUFeaturesFromART(vixl::aarch64::MacroAssembler* vixl_masm_,
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const Arm64InstructionSetFeatures* art_features) {
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// Retrieve already initialized default features of vixl.
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vixl::CPUFeatures* features = vixl_masm_->GetCPUFeatures();
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DCHECK(features->Has(vixl::CPUFeatures::kFP));
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DCHECK(features->Has(vixl::CPUFeatures::kNEON));
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DCHECK(art_features != nullptr);
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if (art_features->HasCRC()) {
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features->Combine(vixl::CPUFeatures::kCRC32);
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}
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if (art_features->HasDotProd()) {
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features->Combine(vixl::CPUFeatures::kDotProduct);
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}
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if (art_features->HasFP16()) {
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features->Combine(vixl::CPUFeatures::kFPHalf);
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features->Combine(vixl::CPUFeatures::kNEONHalf);
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}
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if (art_features->HasLSE()) {
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features->Combine(vixl::CPUFeatures::kAtomics);
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}
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if (art_features->HasSVE()) {
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features->Combine(vixl::CPUFeatures::kSVE);
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}
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}
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Arm64Assembler::Arm64Assembler(ArenaAllocator* allocator,
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const Arm64InstructionSetFeatures* art_features)
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: Assembler(allocator) {
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if (art_features != nullptr) {
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SetVIXLCPUFeaturesFromART(&vixl_masm_, art_features);
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}
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}
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void Arm64Assembler::FinalizeCode() {
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___ FinalizeCode();
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}
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size_t Arm64Assembler::CodeSize() const {
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return vixl_masm_.GetSizeOfCodeGenerated();
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}
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const uint8_t* Arm64Assembler::CodeBufferBaseAddress() const {
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return vixl_masm_.GetBuffer().GetStartAddress<const uint8_t*>();
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}
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void Arm64Assembler::FinalizeInstructions(const MemoryRegion& region) {
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// Copy the instructions from the buffer.
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MemoryRegion from(vixl_masm_.GetBuffer()->GetStartAddress<void*>(), CodeSize());
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region.CopyFrom(0, from);
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}
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void Arm64Assembler::LoadRawPtr(ManagedRegister m_dst, ManagedRegister m_base, Offset offs) {
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Arm64ManagedRegister dst = m_dst.AsArm64();
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Arm64ManagedRegister base = m_base.AsArm64();
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CHECK(dst.IsXRegister() && base.IsXRegister());
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// Remove dst and base form the temp list - higher level API uses IP1, IP0.
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UseScratchRegisterScope temps(&vixl_masm_);
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temps.Exclude(reg_x(dst.AsXRegister()), reg_x(base.AsXRegister()));
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___ Ldr(reg_x(dst.AsXRegister()), MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value()));
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}
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void Arm64Assembler::JumpTo(ManagedRegister m_base, Offset offs, ManagedRegister m_scratch) {
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Arm64ManagedRegister base = m_base.AsArm64();
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Arm64ManagedRegister scratch = m_scratch.AsArm64();
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CHECK(base.IsXRegister()) << base;
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CHECK(scratch.IsXRegister()) << scratch;
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// Remove base and scratch form the temp list - higher level API uses IP1, IP0.
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UseScratchRegisterScope temps(&vixl_masm_);
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temps.Exclude(reg_x(base.AsXRegister()), reg_x(scratch.AsXRegister()));
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___ Ldr(reg_x(scratch.AsXRegister()), MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value()));
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___ Br(reg_x(scratch.AsXRegister()));
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}
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void Arm64Assembler::SpillRegisters(CPURegList registers, int offset) {
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int size = registers.GetRegisterSizeInBytes();
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const Register sp = vixl_masm_.StackPointer();
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// Since we are operating on register pairs, we would like to align on
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// double the standard size; on the other hand, we don't want to insert
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// an extra store, which will happen if the number of registers is even.
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if (!IsAlignedParam(offset, 2 * size) && registers.GetCount() % 2 != 0) {
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const CPURegister& dst0 = registers.PopLowestIndex();
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___ Str(dst0, MemOperand(sp, offset));
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cfi_.RelOffset(DWARFReg(dst0), offset);
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offset += size;
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}
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while (registers.GetCount() >= 2) {
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const CPURegister& dst0 = registers.PopLowestIndex();
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const CPURegister& dst1 = registers.PopLowestIndex();
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___ Stp(dst0, dst1, MemOperand(sp, offset));
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cfi_.RelOffset(DWARFReg(dst0), offset);
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cfi_.RelOffset(DWARFReg(dst1), offset + size);
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offset += 2 * size;
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}
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if (!registers.IsEmpty()) {
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const CPURegister& dst0 = registers.PopLowestIndex();
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___ Str(dst0, MemOperand(sp, offset));
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cfi_.RelOffset(DWARFReg(dst0), offset);
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}
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DCHECK(registers.IsEmpty());
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}
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void Arm64Assembler::UnspillRegisters(CPURegList registers, int offset) {
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int size = registers.GetRegisterSizeInBytes();
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const Register sp = vixl_masm_.StackPointer();
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// Be consistent with the logic for spilling registers.
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if (!IsAlignedParam(offset, 2 * size) && registers.GetCount() % 2 != 0) {
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const CPURegister& dst0 = registers.PopLowestIndex();
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___ Ldr(dst0, MemOperand(sp, offset));
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cfi_.Restore(DWARFReg(dst0));
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offset += size;
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}
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while (registers.GetCount() >= 2) {
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const CPURegister& dst0 = registers.PopLowestIndex();
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const CPURegister& dst1 = registers.PopLowestIndex();
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___ Ldp(dst0, dst1, MemOperand(sp, offset));
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cfi_.Restore(DWARFReg(dst0));
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cfi_.Restore(DWARFReg(dst1));
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offset += 2 * size;
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}
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if (!registers.IsEmpty()) {
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const CPURegister& dst0 = registers.PopLowestIndex();
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___ Ldr(dst0, MemOperand(sp, offset));
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cfi_.Restore(DWARFReg(dst0));
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}
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DCHECK(registers.IsEmpty());
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}
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void Arm64Assembler::PoisonHeapReference(Register reg) {
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DCHECK(reg.IsW());
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// reg = -reg.
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___ Neg(reg, Operand(reg));
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}
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void Arm64Assembler::UnpoisonHeapReference(Register reg) {
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DCHECK(reg.IsW());
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// reg = -reg.
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___ Neg(reg, Operand(reg));
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}
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void Arm64Assembler::MaybePoisonHeapReference(Register reg) {
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if (kPoisonHeapReferences) {
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PoisonHeapReference(reg);
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}
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}
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void Arm64Assembler::MaybeUnpoisonHeapReference(Register reg) {
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if (kPoisonHeapReferences) {
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UnpoisonHeapReference(reg);
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}
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}
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void Arm64Assembler::GenerateMarkingRegisterCheck(Register temp, int code) {
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// The Marking Register is only used in the Baker read barrier configuration.
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DCHECK(kEmitCompilerReadBarrier);
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DCHECK(kUseBakerReadBarrier);
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vixl::aarch64::Register mr = reg_x(MR); // Marking Register.
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vixl::aarch64::Register tr = reg_x(TR); // Thread Register.
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vixl::aarch64::Label mr_is_ok;
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// temp = self.tls32_.is.gc_marking
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___ Ldr(temp, MemOperand(tr, Thread::IsGcMarkingOffset<kArm64PointerSize>().Int32Value()));
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// Check that mr == self.tls32_.is.gc_marking.
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___ Cmp(mr.W(), temp);
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___ B(eq, &mr_is_ok);
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___ Brk(code);
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___ Bind(&mr_is_ok);
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}
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#undef ___
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} // namespace arm64
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} // namespace art
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