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1082 lines
39 KiB
1082 lines
39 KiB
/*
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* Copyright (C) 2014 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_
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#define ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_
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#include <vector>
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#include "arch/x86_64/instruction_set_features_x86_64.h"
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#include "base/arena_containers.h"
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#include "base/array_ref.h"
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#include "base/bit_utils.h"
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#include "base/globals.h"
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#include "base/macros.h"
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#include "constants_x86_64.h"
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#include "heap_poisoning.h"
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#include "managed_register_x86_64.h"
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#include "offsets.h"
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#include "utils/assembler.h"
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#include "utils/jni_macro_assembler.h"
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namespace art {
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namespace x86_64 {
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// Encodes an immediate value for operands.
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//
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// Note: Immediates can be 64b on x86-64 for certain instructions, but are often restricted
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// to 32b.
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//
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// Note: As we support cross-compilation, the value type must be int64_t. Please be aware of
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// conversion rules in expressions regarding negation, especially size_t on 32b.
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class Immediate : public ValueObject {
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public:
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explicit Immediate(int64_t value_in) : value_(value_in) {}
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int64_t value() const { return value_; }
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bool is_int8() const { return IsInt<8>(value_); }
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bool is_uint8() const { return IsUint<8>(value_); }
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bool is_int16() const { return IsInt<16>(value_); }
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bool is_uint16() const { return IsUint<16>(value_); }
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bool is_int32() const { return IsInt<32>(value_); }
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private:
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const int64_t value_;
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};
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class Operand : public ValueObject {
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public:
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uint8_t mod() const {
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return (encoding_at(0) >> 6) & 3;
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}
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Register rm() const {
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return static_cast<Register>(encoding_at(0) & 7);
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}
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ScaleFactor scale() const {
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return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3);
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}
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Register index() const {
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return static_cast<Register>((encoding_at(1) >> 3) & 7);
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}
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Register base() const {
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return static_cast<Register>(encoding_at(1) & 7);
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}
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CpuRegister cpu_rm() const {
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int ext = (rex_ & 1) != 0 ? x86_64::R8 : x86_64::RAX;
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return static_cast<CpuRegister>(rm() + ext);
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}
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CpuRegister cpu_index() const {
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int ext = (rex_ & 2) != 0 ? x86_64::R8 : x86_64::RAX;
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return static_cast<CpuRegister>(index() + ext);
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}
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CpuRegister cpu_base() const {
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int ext = (rex_ & 1) != 0 ? x86_64::R8 : x86_64::RAX;
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return static_cast<CpuRegister>(base() + ext);
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}
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uint8_t rex() const {
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return rex_;
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}
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int8_t disp8() const {
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CHECK_GE(length_, 2);
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return static_cast<int8_t>(encoding_[length_ - 1]);
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}
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int32_t disp32() const {
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CHECK_GE(length_, 5);
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int32_t value;
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memcpy(&value, &encoding_[length_ - 4], sizeof(value));
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return value;
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}
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bool IsRegister(CpuRegister reg) const {
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return ((encoding_[0] & 0xF8) == 0xC0) // Addressing mode is register only.
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&& ((encoding_[0] & 0x07) == reg.LowBits()) // Register codes match.
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&& (reg.NeedsRex() == ((rex_ & 1) != 0)); // REX.000B bits match.
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}
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AssemblerFixup* GetFixup() const {
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return fixup_;
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}
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protected:
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// Operand can be sub classed (e.g: Address).
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Operand() : rex_(0), length_(0), fixup_(nullptr) { }
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void SetModRM(uint8_t mod_in, CpuRegister rm_in) {
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CHECK_EQ(mod_in & ~3, 0);
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if (rm_in.NeedsRex()) {
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rex_ |= 0x41; // REX.000B
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}
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encoding_[0] = (mod_in << 6) | rm_in.LowBits();
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length_ = 1;
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}
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void SetSIB(ScaleFactor scale_in, CpuRegister index_in, CpuRegister base_in) {
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CHECK_EQ(length_, 1);
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CHECK_EQ(scale_in & ~3, 0);
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if (base_in.NeedsRex()) {
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rex_ |= 0x41; // REX.000B
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}
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if (index_in.NeedsRex()) {
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rex_ |= 0x42; // REX.00X0
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}
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encoding_[1] = (scale_in << 6) | (static_cast<uint8_t>(index_in.LowBits()) << 3) |
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static_cast<uint8_t>(base_in.LowBits());
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length_ = 2;
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}
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void SetDisp8(int8_t disp) {
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CHECK(length_ == 1 || length_ == 2);
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encoding_[length_++] = static_cast<uint8_t>(disp);
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}
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void SetDisp32(int32_t disp) {
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CHECK(length_ == 1 || length_ == 2);
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int disp_size = sizeof(disp);
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memmove(&encoding_[length_], &disp, disp_size);
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length_ += disp_size;
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}
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void SetFixup(AssemblerFixup* fixup) {
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fixup_ = fixup;
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}
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private:
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uint8_t rex_;
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uint8_t length_;
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uint8_t encoding_[6];
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AssemblerFixup* fixup_;
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explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); }
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// Get the operand encoding byte at the given index.
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uint8_t encoding_at(int index_in) const {
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CHECK_GE(index_in, 0);
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CHECK_LT(index_in, length_);
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return encoding_[index_in];
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}
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friend class X86_64Assembler;
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};
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class Address : public Operand {
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public:
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Address(CpuRegister base_in, int32_t disp) {
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Init(base_in, disp);
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}
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Address(CpuRegister base_in, Offset disp) {
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Init(base_in, disp.Int32Value());
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}
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Address(CpuRegister base_in, FrameOffset disp) {
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CHECK_EQ(base_in.AsRegister(), RSP);
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Init(CpuRegister(RSP), disp.Int32Value());
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}
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Address(CpuRegister base_in, MemberOffset disp) {
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Init(base_in, disp.Int32Value());
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}
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void Init(CpuRegister base_in, int32_t disp) {
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if (disp == 0 && base_in.LowBits() != RBP) {
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SetModRM(0, base_in);
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if (base_in.LowBits() == RSP) {
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SetSIB(TIMES_1, CpuRegister(RSP), base_in);
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}
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} else if (disp >= -128 && disp <= 127) {
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SetModRM(1, base_in);
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if (base_in.LowBits() == RSP) {
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SetSIB(TIMES_1, CpuRegister(RSP), base_in);
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}
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SetDisp8(disp);
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} else {
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SetModRM(2, base_in);
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if (base_in.LowBits() == RSP) {
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SetSIB(TIMES_1, CpuRegister(RSP), base_in);
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}
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SetDisp32(disp);
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}
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}
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Address(CpuRegister index_in, ScaleFactor scale_in, int32_t disp) {
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CHECK_NE(index_in.AsRegister(), RSP); // Illegal addressing mode.
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SetModRM(0, CpuRegister(RSP));
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SetSIB(scale_in, index_in, CpuRegister(RBP));
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SetDisp32(disp);
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}
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Address(CpuRegister base_in, CpuRegister index_in, ScaleFactor scale_in, int32_t disp) {
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CHECK_NE(index_in.AsRegister(), RSP); // Illegal addressing mode.
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if (disp == 0 && base_in.LowBits() != RBP) {
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SetModRM(0, CpuRegister(RSP));
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SetSIB(scale_in, index_in, base_in);
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} else if (disp >= -128 && disp <= 127) {
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SetModRM(1, CpuRegister(RSP));
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SetSIB(scale_in, index_in, base_in);
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SetDisp8(disp);
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} else {
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SetModRM(2, CpuRegister(RSP));
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SetSIB(scale_in, index_in, base_in);
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SetDisp32(disp);
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}
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}
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// If no_rip is true then the Absolute address isn't RIP relative.
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static Address Absolute(uintptr_t addr, bool no_rip = false) {
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Address result;
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if (no_rip) {
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result.SetModRM(0, CpuRegister(RSP));
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result.SetSIB(TIMES_1, CpuRegister(RSP), CpuRegister(RBP));
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result.SetDisp32(addr);
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} else {
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// RIP addressing is done using RBP as the base register.
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// The value in RBP isn't used. Instead the offset is added to RIP.
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result.SetModRM(0, CpuRegister(RBP));
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result.SetDisp32(addr);
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}
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return result;
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}
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// An RIP relative address that will be fixed up later.
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static Address RIP(AssemblerFixup* fixup) {
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Address result;
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// RIP addressing is done using RBP as the base register.
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// The value in RBP isn't used. Instead the offset is added to RIP.
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result.SetModRM(0, CpuRegister(RBP));
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result.SetDisp32(0);
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result.SetFixup(fixup);
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return result;
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}
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// If no_rip is true then the Absolute address isn't RIP relative.
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static Address Absolute(ThreadOffset64 addr, bool no_rip = false) {
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return Absolute(addr.Int32Value(), no_rip);
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}
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private:
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Address() {}
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};
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std::ostream& operator<<(std::ostream& os, const Address& addr);
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/**
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* Class to handle constant area values.
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*/
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class ConstantArea {
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public:
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explicit ConstantArea(ArenaAllocator* allocator)
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: buffer_(allocator->Adapter(kArenaAllocAssembler)) {}
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// Add a double to the constant area, returning the offset into
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// the constant area where the literal resides.
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size_t AddDouble(double v);
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// Add a float to the constant area, returning the offset into
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// the constant area where the literal resides.
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size_t AddFloat(float v);
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// Add an int32_t to the constant area, returning the offset into
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// the constant area where the literal resides.
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size_t AddInt32(int32_t v);
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// Add an int32_t to the end of the constant area, returning the offset into
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// the constant area where the literal resides.
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size_t AppendInt32(int32_t v);
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// Add an int64_t to the constant area, returning the offset into
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// the constant area where the literal resides.
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size_t AddInt64(int64_t v);
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size_t GetSize() const {
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return buffer_.size() * elem_size_;
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}
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ArrayRef<const int32_t> GetBuffer() const {
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return ArrayRef<const int32_t>(buffer_);
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}
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private:
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static constexpr size_t elem_size_ = sizeof(int32_t);
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ArenaVector<int32_t> buffer_;
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};
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// This is equivalent to the Label class, used in a slightly different context. We
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// inherit the functionality of the Label class, but prevent unintended
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// derived-to-base conversions by making the base class private.
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class NearLabel : private Label {
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public:
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NearLabel() : Label() {}
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// Expose the Label routines that we need.
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using Label::Position;
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using Label::LinkPosition;
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using Label::IsBound;
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using Label::IsUnused;
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using Label::IsLinked;
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private:
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using Label::BindTo;
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using Label::LinkTo;
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friend class x86_64::X86_64Assembler;
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DISALLOW_COPY_AND_ASSIGN(NearLabel);
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};
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class X86_64Assembler final : public Assembler {
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public:
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explicit X86_64Assembler(ArenaAllocator* allocator,
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const X86_64InstructionSetFeatures* instruction_set_features = nullptr)
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: Assembler(allocator),
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constant_area_(allocator),
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has_AVX_(instruction_set_features != nullptr ? instruction_set_features->HasAVX(): false),
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has_AVX2_(instruction_set_features != nullptr ? instruction_set_features->HasAVX2() : false) {}
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virtual ~X86_64Assembler() {}
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/*
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* Emit Machine Instructions.
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*/
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void call(CpuRegister reg);
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void call(const Address& address);
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void call(Label* label);
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void pushq(CpuRegister reg);
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void pushq(const Address& address);
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void pushq(const Immediate& imm);
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void popq(CpuRegister reg);
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void popq(const Address& address);
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void movq(CpuRegister dst, const Immediate& src);
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void movl(CpuRegister dst, const Immediate& src);
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void movq(CpuRegister dst, CpuRegister src);
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void movl(CpuRegister dst, CpuRegister src);
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void movntl(const Address& dst, CpuRegister src);
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void movntq(const Address& dst, CpuRegister src);
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void movq(CpuRegister dst, const Address& src);
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void movl(CpuRegister dst, const Address& src);
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void movq(const Address& dst, CpuRegister src);
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void movq(const Address& dst, const Immediate& imm);
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void movl(const Address& dst, CpuRegister src);
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void movl(const Address& dst, const Immediate& imm);
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void cmov(Condition c, CpuRegister dst, CpuRegister src); // This is the 64b version.
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void cmov(Condition c, CpuRegister dst, CpuRegister src, bool is64bit);
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void cmov(Condition c, CpuRegister dst, const Address& src, bool is64bit);
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void movzxb(CpuRegister dst, CpuRegister src);
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void movzxb(CpuRegister dst, const Address& src);
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void movsxb(CpuRegister dst, CpuRegister src);
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void movsxb(CpuRegister dst, const Address& src);
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void movb(CpuRegister dst, const Address& src);
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void movb(const Address& dst, CpuRegister src);
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void movb(const Address& dst, const Immediate& imm);
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void movzxw(CpuRegister dst, CpuRegister src);
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void movzxw(CpuRegister dst, const Address& src);
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void movsxw(CpuRegister dst, CpuRegister src);
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void movsxw(CpuRegister dst, const Address& src);
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void movw(CpuRegister dst, const Address& src);
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void movw(const Address& dst, CpuRegister src);
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void movw(const Address& dst, const Immediate& imm);
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void leaq(CpuRegister dst, const Address& src);
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void leal(CpuRegister dst, const Address& src);
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void movaps(XmmRegister dst, XmmRegister src); // move
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void movaps(XmmRegister dst, const Address& src); // load aligned
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void movups(XmmRegister dst, const Address& src); // load unaligned
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void movaps(const Address& dst, XmmRegister src); // store aligned
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void movups(const Address& dst, XmmRegister src); // store unaligned
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void vmovaps(XmmRegister dst, XmmRegister src); // move
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void vmovaps(XmmRegister dst, const Address& src); // load aligned
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void vmovaps(const Address& dst, XmmRegister src); // store aligned
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void vmovups(XmmRegister dst, const Address& src); // load unaligned
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void vmovups(const Address& dst, XmmRegister src); // store unaligned
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void movss(XmmRegister dst, const Address& src);
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void movss(const Address& dst, XmmRegister src);
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void movss(XmmRegister dst, XmmRegister src);
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void movsxd(CpuRegister dst, CpuRegister src);
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void movsxd(CpuRegister dst, const Address& src);
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void movd(XmmRegister dst, CpuRegister src); // Note: this is the r64 version, formally movq.
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void movd(CpuRegister dst, XmmRegister src); // Note: this is the r64 version, formally movq.
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void movd(XmmRegister dst, CpuRegister src, bool is64bit);
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void movd(CpuRegister dst, XmmRegister src, bool is64bit);
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void addss(XmmRegister dst, XmmRegister src);
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void addss(XmmRegister dst, const Address& src);
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void subss(XmmRegister dst, XmmRegister src);
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void subss(XmmRegister dst, const Address& src);
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void mulss(XmmRegister dst, XmmRegister src);
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void mulss(XmmRegister dst, const Address& src);
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void divss(XmmRegister dst, XmmRegister src);
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void divss(XmmRegister dst, const Address& src);
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void addps(XmmRegister dst, XmmRegister src); // no addr variant (for now)
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void subps(XmmRegister dst, XmmRegister src);
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void mulps(XmmRegister dst, XmmRegister src);
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void divps(XmmRegister dst, XmmRegister src);
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void vmulps(XmmRegister dst, XmmRegister src1, XmmRegister src2);
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void vmulpd(XmmRegister dst, XmmRegister src1, XmmRegister src2);
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void vdivps(XmmRegister dst, XmmRegister src1, XmmRegister src2);
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void vdivpd(XmmRegister dst, XmmRegister src1, XmmRegister src2);
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void vaddps(XmmRegister dst, XmmRegister add_left, XmmRegister add_right);
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void vsubps(XmmRegister dst, XmmRegister add_left, XmmRegister add_right);
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void vsubpd(XmmRegister dst, XmmRegister add_left, XmmRegister add_right);
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void vaddpd(XmmRegister dst, XmmRegister add_left, XmmRegister add_right);
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void movapd(XmmRegister dst, XmmRegister src); // move
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void movapd(XmmRegister dst, const Address& src); // load aligned
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void movupd(XmmRegister dst, const Address& src); // load unaligned
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void movapd(const Address& dst, XmmRegister src); // store aligned
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void movupd(const Address& dst, XmmRegister src); // store unaligned
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void vmovapd(XmmRegister dst, XmmRegister src); // move
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void vmovapd(XmmRegister dst, const Address& src); // load aligned
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void vmovapd(const Address& dst, XmmRegister src); // store aligned
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void vmovupd(XmmRegister dst, const Address& src); // load unaligned
|
|
void vmovupd(const Address& dst, XmmRegister src); // store unaligned
|
|
|
|
void movsd(XmmRegister dst, const Address& src);
|
|
void movsd(const Address& dst, XmmRegister src);
|
|
void movsd(XmmRegister dst, XmmRegister src);
|
|
|
|
void addsd(XmmRegister dst, XmmRegister src);
|
|
void addsd(XmmRegister dst, const Address& src);
|
|
void subsd(XmmRegister dst, XmmRegister src);
|
|
void subsd(XmmRegister dst, const Address& src);
|
|
void mulsd(XmmRegister dst, XmmRegister src);
|
|
void mulsd(XmmRegister dst, const Address& src);
|
|
void divsd(XmmRegister dst, XmmRegister src);
|
|
void divsd(XmmRegister dst, const Address& src);
|
|
|
|
void addpd(XmmRegister dst, XmmRegister src); // no addr variant (for now)
|
|
void subpd(XmmRegister dst, XmmRegister src);
|
|
void mulpd(XmmRegister dst, XmmRegister src);
|
|
void divpd(XmmRegister dst, XmmRegister src);
|
|
|
|
void movdqa(XmmRegister dst, XmmRegister src); // move
|
|
void movdqa(XmmRegister dst, const Address& src); // load aligned
|
|
void movdqu(XmmRegister dst, const Address& src); // load unaligned
|
|
void movdqa(const Address& dst, XmmRegister src); // store aligned
|
|
void movdqu(const Address& dst, XmmRegister src); // store unaligned
|
|
|
|
void vmovdqa(XmmRegister dst, XmmRegister src); // move
|
|
void vmovdqa(XmmRegister dst, const Address& src); // load aligned
|
|
void vmovdqa(const Address& dst, XmmRegister src); // store aligned
|
|
void vmovdqu(XmmRegister dst, const Address& src); // load unaligned
|
|
void vmovdqu(const Address& dst, XmmRegister src); // store unaligned
|
|
|
|
void paddb(XmmRegister dst, XmmRegister src); // no addr variant (for now)
|
|
void psubb(XmmRegister dst, XmmRegister src);
|
|
|
|
void vpaddb(XmmRegister dst, XmmRegister add_left, XmmRegister add_right);
|
|
void vpaddw(XmmRegister dst, XmmRegister add_left, XmmRegister add_right);
|
|
|
|
void paddw(XmmRegister dst, XmmRegister src);
|
|
void psubw(XmmRegister dst, XmmRegister src);
|
|
void pmullw(XmmRegister dst, XmmRegister src);
|
|
void vpmullw(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
|
|
void vpsubb(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
void vpsubw(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
void vpsubd(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
|
|
void paddd(XmmRegister dst, XmmRegister src);
|
|
void psubd(XmmRegister dst, XmmRegister src);
|
|
void pmulld(XmmRegister dst, XmmRegister src);
|
|
void vpmulld(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
|
|
void vpaddd(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
|
|
void paddq(XmmRegister dst, XmmRegister src);
|
|
void psubq(XmmRegister dst, XmmRegister src);
|
|
|
|
void vpaddq(XmmRegister dst, XmmRegister add_left, XmmRegister add_right);
|
|
void vpsubq(XmmRegister dst, XmmRegister add_left, XmmRegister add_right);
|
|
|
|
void paddusb(XmmRegister dst, XmmRegister src);
|
|
void paddsb(XmmRegister dst, XmmRegister src);
|
|
void paddusw(XmmRegister dst, XmmRegister src);
|
|
void paddsw(XmmRegister dst, XmmRegister src);
|
|
void psubusb(XmmRegister dst, XmmRegister src);
|
|
void psubsb(XmmRegister dst, XmmRegister src);
|
|
void psubusw(XmmRegister dst, XmmRegister src);
|
|
void psubsw(XmmRegister dst, XmmRegister src);
|
|
|
|
void cvtsi2ss(XmmRegister dst, CpuRegister src); // Note: this is the r/m32 version.
|
|
void cvtsi2ss(XmmRegister dst, CpuRegister src, bool is64bit);
|
|
void cvtsi2ss(XmmRegister dst, const Address& src, bool is64bit);
|
|
void cvtsi2sd(XmmRegister dst, CpuRegister src); // Note: this is the r/m32 version.
|
|
void cvtsi2sd(XmmRegister dst, CpuRegister src, bool is64bit);
|
|
void cvtsi2sd(XmmRegister dst, const Address& src, bool is64bit);
|
|
|
|
void cvtss2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version.
|
|
void cvtss2sd(XmmRegister dst, XmmRegister src);
|
|
void cvtss2sd(XmmRegister dst, const Address& src);
|
|
|
|
void cvtsd2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version.
|
|
void cvtsd2ss(XmmRegister dst, XmmRegister src);
|
|
void cvtsd2ss(XmmRegister dst, const Address& src);
|
|
|
|
void cvttss2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version.
|
|
void cvttss2si(CpuRegister dst, XmmRegister src, bool is64bit);
|
|
void cvttsd2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version.
|
|
void cvttsd2si(CpuRegister dst, XmmRegister src, bool is64bit);
|
|
|
|
void cvtdq2ps(XmmRegister dst, XmmRegister src);
|
|
void cvtdq2pd(XmmRegister dst, XmmRegister src);
|
|
|
|
void comiss(XmmRegister a, XmmRegister b);
|
|
void comiss(XmmRegister a, const Address& b);
|
|
void comisd(XmmRegister a, XmmRegister b);
|
|
void comisd(XmmRegister a, const Address& b);
|
|
void ucomiss(XmmRegister a, XmmRegister b);
|
|
void ucomiss(XmmRegister a, const Address& b);
|
|
void ucomisd(XmmRegister a, XmmRegister b);
|
|
void ucomisd(XmmRegister a, const Address& b);
|
|
|
|
void roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm);
|
|
void roundss(XmmRegister dst, XmmRegister src, const Immediate& imm);
|
|
|
|
void sqrtsd(XmmRegister dst, XmmRegister src);
|
|
void sqrtss(XmmRegister dst, XmmRegister src);
|
|
|
|
void xorpd(XmmRegister dst, const Address& src);
|
|
void xorpd(XmmRegister dst, XmmRegister src);
|
|
void xorps(XmmRegister dst, const Address& src);
|
|
void xorps(XmmRegister dst, XmmRegister src);
|
|
void pxor(XmmRegister dst, XmmRegister src); // no addr variant (for now)
|
|
void vpxor(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
void vxorps(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
void vxorpd(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
|
|
void andpd(XmmRegister dst, const Address& src);
|
|
void andpd(XmmRegister dst, XmmRegister src);
|
|
void andps(XmmRegister dst, XmmRegister src); // no addr variant (for now)
|
|
void pand(XmmRegister dst, XmmRegister src);
|
|
void vpand(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
void vandps(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
void vandpd(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
|
|
void andn(CpuRegister dst, CpuRegister src1, CpuRegister src2);
|
|
void andnpd(XmmRegister dst, XmmRegister src); // no addr variant (for now)
|
|
void andnps(XmmRegister dst, XmmRegister src);
|
|
void pandn(XmmRegister dst, XmmRegister src);
|
|
void vpandn(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
void vandnps(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
void vandnpd(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
|
|
void orpd(XmmRegister dst, XmmRegister src); // no addr variant (for now)
|
|
void orps(XmmRegister dst, XmmRegister src);
|
|
void por(XmmRegister dst, XmmRegister src);
|
|
void vpor(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
void vorps(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
void vorpd(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
|
|
void pavgb(XmmRegister dst, XmmRegister src); // no addr variant (for now)
|
|
void pavgw(XmmRegister dst, XmmRegister src);
|
|
void psadbw(XmmRegister dst, XmmRegister src);
|
|
void pmaddwd(XmmRegister dst, XmmRegister src);
|
|
void vpmaddwd(XmmRegister dst, XmmRegister src1, XmmRegister src2);
|
|
void phaddw(XmmRegister dst, XmmRegister src);
|
|
void phaddd(XmmRegister dst, XmmRegister src);
|
|
void haddps(XmmRegister dst, XmmRegister src);
|
|
void haddpd(XmmRegister dst, XmmRegister src);
|
|
void phsubw(XmmRegister dst, XmmRegister src);
|
|
void phsubd(XmmRegister dst, XmmRegister src);
|
|
void hsubps(XmmRegister dst, XmmRegister src);
|
|
void hsubpd(XmmRegister dst, XmmRegister src);
|
|
|
|
void pminsb(XmmRegister dst, XmmRegister src); // no addr variant (for now)
|
|
void pmaxsb(XmmRegister dst, XmmRegister src);
|
|
void pminsw(XmmRegister dst, XmmRegister src);
|
|
void pmaxsw(XmmRegister dst, XmmRegister src);
|
|
void pminsd(XmmRegister dst, XmmRegister src);
|
|
void pmaxsd(XmmRegister dst, XmmRegister src);
|
|
|
|
void pminub(XmmRegister dst, XmmRegister src); // no addr variant (for now)
|
|
void pmaxub(XmmRegister dst, XmmRegister src);
|
|
void pminuw(XmmRegister dst, XmmRegister src);
|
|
void pmaxuw(XmmRegister dst, XmmRegister src);
|
|
void pminud(XmmRegister dst, XmmRegister src);
|
|
void pmaxud(XmmRegister dst, XmmRegister src);
|
|
|
|
void minps(XmmRegister dst, XmmRegister src); // no addr variant (for now)
|
|
void maxps(XmmRegister dst, XmmRegister src);
|
|
void minpd(XmmRegister dst, XmmRegister src);
|
|
void maxpd(XmmRegister dst, XmmRegister src);
|
|
|
|
void pcmpeqb(XmmRegister dst, XmmRegister src);
|
|
void pcmpeqw(XmmRegister dst, XmmRegister src);
|
|
void pcmpeqd(XmmRegister dst, XmmRegister src);
|
|
void pcmpeqq(XmmRegister dst, XmmRegister src);
|
|
|
|
void pcmpgtb(XmmRegister dst, XmmRegister src);
|
|
void pcmpgtw(XmmRegister dst, XmmRegister src);
|
|
void pcmpgtd(XmmRegister dst, XmmRegister src);
|
|
void pcmpgtq(XmmRegister dst, XmmRegister src); // SSE4.2
|
|
|
|
void shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm);
|
|
void shufps(XmmRegister dst, XmmRegister src, const Immediate& imm);
|
|
void pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm);
|
|
|
|
void punpcklbw(XmmRegister dst, XmmRegister src);
|
|
void punpcklwd(XmmRegister dst, XmmRegister src);
|
|
void punpckldq(XmmRegister dst, XmmRegister src);
|
|
void punpcklqdq(XmmRegister dst, XmmRegister src);
|
|
|
|
void punpckhbw(XmmRegister dst, XmmRegister src);
|
|
void punpckhwd(XmmRegister dst, XmmRegister src);
|
|
void punpckhdq(XmmRegister dst, XmmRegister src);
|
|
void punpckhqdq(XmmRegister dst, XmmRegister src);
|
|
|
|
void psllw(XmmRegister reg, const Immediate& shift_count);
|
|
void pslld(XmmRegister reg, const Immediate& shift_count);
|
|
void psllq(XmmRegister reg, const Immediate& shift_count);
|
|
|
|
void psraw(XmmRegister reg, const Immediate& shift_count);
|
|
void psrad(XmmRegister reg, const Immediate& shift_count);
|
|
// no psraq
|
|
|
|
void psrlw(XmmRegister reg, const Immediate& shift_count);
|
|
void psrld(XmmRegister reg, const Immediate& shift_count);
|
|
void psrlq(XmmRegister reg, const Immediate& shift_count);
|
|
void psrldq(XmmRegister reg, const Immediate& shift_count);
|
|
|
|
void flds(const Address& src);
|
|
void fstps(const Address& dst);
|
|
void fsts(const Address& dst);
|
|
|
|
void fldl(const Address& src);
|
|
void fstpl(const Address& dst);
|
|
void fstl(const Address& dst);
|
|
|
|
void fstsw();
|
|
|
|
void fucompp();
|
|
|
|
void fnstcw(const Address& dst);
|
|
void fldcw(const Address& src);
|
|
|
|
void fistpl(const Address& dst);
|
|
void fistps(const Address& dst);
|
|
void fildl(const Address& src);
|
|
void filds(const Address& src);
|
|
|
|
void fincstp();
|
|
void ffree(const Immediate& index);
|
|
|
|
void fsin();
|
|
void fcos();
|
|
void fptan();
|
|
void fprem();
|
|
|
|
void xchgl(CpuRegister dst, CpuRegister src);
|
|
void xchgq(CpuRegister dst, CpuRegister src);
|
|
void xchgl(CpuRegister reg, const Address& address);
|
|
|
|
void cmpb(const Address& address, const Immediate& imm);
|
|
void cmpw(const Address& address, const Immediate& imm);
|
|
|
|
void cmpl(CpuRegister reg, const Immediate& imm);
|
|
void cmpl(CpuRegister reg0, CpuRegister reg1);
|
|
void cmpl(CpuRegister reg, const Address& address);
|
|
void cmpl(const Address& address, CpuRegister reg);
|
|
void cmpl(const Address& address, const Immediate& imm);
|
|
|
|
void cmpq(CpuRegister reg0, CpuRegister reg1);
|
|
void cmpq(CpuRegister reg0, const Immediate& imm);
|
|
void cmpq(CpuRegister reg0, const Address& address);
|
|
void cmpq(const Address& address, const Immediate& imm);
|
|
|
|
void testl(CpuRegister reg1, CpuRegister reg2);
|
|
void testl(CpuRegister reg, const Address& address);
|
|
void testl(CpuRegister reg, const Immediate& imm);
|
|
|
|
void testq(CpuRegister reg1, CpuRegister reg2);
|
|
void testq(CpuRegister reg, const Address& address);
|
|
|
|
void testb(const Address& address, const Immediate& imm);
|
|
void testl(const Address& address, const Immediate& imm);
|
|
|
|
void andl(CpuRegister dst, const Immediate& imm);
|
|
void andl(CpuRegister dst, CpuRegister src);
|
|
void andl(CpuRegister reg, const Address& address);
|
|
void andq(CpuRegister dst, const Immediate& imm);
|
|
void andq(CpuRegister dst, CpuRegister src);
|
|
void andq(CpuRegister reg, const Address& address);
|
|
void andw(const Address& address, const Immediate& imm);
|
|
|
|
void orl(CpuRegister dst, const Immediate& imm);
|
|
void orl(CpuRegister dst, CpuRegister src);
|
|
void orl(CpuRegister reg, const Address& address);
|
|
void orq(CpuRegister dst, CpuRegister src);
|
|
void orq(CpuRegister dst, const Immediate& imm);
|
|
void orq(CpuRegister reg, const Address& address);
|
|
|
|
void xorl(CpuRegister dst, CpuRegister src);
|
|
void xorl(CpuRegister dst, const Immediate& imm);
|
|
void xorl(CpuRegister reg, const Address& address);
|
|
void xorq(CpuRegister dst, const Immediate& imm);
|
|
void xorq(CpuRegister dst, CpuRegister src);
|
|
void xorq(CpuRegister reg, const Address& address);
|
|
|
|
void addl(CpuRegister dst, CpuRegister src);
|
|
void addl(CpuRegister reg, const Immediate& imm);
|
|
void addl(CpuRegister reg, const Address& address);
|
|
void addl(const Address& address, CpuRegister reg);
|
|
void addl(const Address& address, const Immediate& imm);
|
|
void addw(const Address& address, const Immediate& imm);
|
|
|
|
void addq(CpuRegister reg, const Immediate& imm);
|
|
void addq(CpuRegister dst, CpuRegister src);
|
|
void addq(CpuRegister dst, const Address& address);
|
|
|
|
void subl(CpuRegister dst, CpuRegister src);
|
|
void subl(CpuRegister reg, const Immediate& imm);
|
|
void subl(CpuRegister reg, const Address& address);
|
|
|
|
void subq(CpuRegister reg, const Immediate& imm);
|
|
void subq(CpuRegister dst, CpuRegister src);
|
|
void subq(CpuRegister dst, const Address& address);
|
|
|
|
void cdq();
|
|
void cqo();
|
|
|
|
void idivl(CpuRegister reg);
|
|
void idivq(CpuRegister reg);
|
|
void divl(CpuRegister reg);
|
|
void divq(CpuRegister reg);
|
|
|
|
void imull(CpuRegister dst, CpuRegister src);
|
|
void imull(CpuRegister reg, const Immediate& imm);
|
|
void imull(CpuRegister dst, CpuRegister src, const Immediate& imm);
|
|
void imull(CpuRegister reg, const Address& address);
|
|
|
|
void imulq(CpuRegister src);
|
|
void imulq(CpuRegister dst, CpuRegister src);
|
|
void imulq(CpuRegister reg, const Immediate& imm);
|
|
void imulq(CpuRegister reg, const Address& address);
|
|
void imulq(CpuRegister dst, CpuRegister reg, const Immediate& imm);
|
|
|
|
void imull(CpuRegister reg);
|
|
void imull(const Address& address);
|
|
|
|
void mull(CpuRegister reg);
|
|
void mull(const Address& address);
|
|
|
|
void shll(CpuRegister reg, const Immediate& imm);
|
|
void shll(CpuRegister operand, CpuRegister shifter);
|
|
void shrl(CpuRegister reg, const Immediate& imm);
|
|
void shrl(CpuRegister operand, CpuRegister shifter);
|
|
void sarl(CpuRegister reg, const Immediate& imm);
|
|
void sarl(CpuRegister operand, CpuRegister shifter);
|
|
|
|
void shlq(CpuRegister reg, const Immediate& imm);
|
|
void shlq(CpuRegister operand, CpuRegister shifter);
|
|
void shrq(CpuRegister reg, const Immediate& imm);
|
|
void shrq(CpuRegister operand, CpuRegister shifter);
|
|
void sarq(CpuRegister reg, const Immediate& imm);
|
|
void sarq(CpuRegister operand, CpuRegister shifter);
|
|
|
|
void negl(CpuRegister reg);
|
|
void negq(CpuRegister reg);
|
|
|
|
void notl(CpuRegister reg);
|
|
void notq(CpuRegister reg);
|
|
|
|
void enter(const Immediate& imm);
|
|
void leave();
|
|
|
|
void ret();
|
|
void ret(const Immediate& imm);
|
|
|
|
void nop();
|
|
void int3();
|
|
void hlt();
|
|
|
|
void j(Condition condition, Label* label);
|
|
void j(Condition condition, NearLabel* label);
|
|
void jrcxz(NearLabel* label);
|
|
|
|
void jmp(CpuRegister reg);
|
|
void jmp(const Address& address);
|
|
void jmp(Label* label);
|
|
void jmp(NearLabel* label);
|
|
|
|
X86_64Assembler* lock();
|
|
void cmpxchgl(const Address& address, CpuRegister reg);
|
|
void cmpxchgq(const Address& address, CpuRegister reg);
|
|
|
|
void mfence();
|
|
|
|
X86_64Assembler* gs();
|
|
|
|
void setcc(Condition condition, CpuRegister dst);
|
|
|
|
void bswapl(CpuRegister dst);
|
|
void bswapq(CpuRegister dst);
|
|
|
|
void bsfl(CpuRegister dst, CpuRegister src);
|
|
void bsfl(CpuRegister dst, const Address& src);
|
|
void bsfq(CpuRegister dst, CpuRegister src);
|
|
void bsfq(CpuRegister dst, const Address& src);
|
|
|
|
void blsi(CpuRegister dst, CpuRegister src); // no addr variant (for now)
|
|
void blsmsk(CpuRegister dst, CpuRegister src); // no addr variant (for now)
|
|
void blsr(CpuRegister dst, CpuRegister src); // no addr variant (for now)
|
|
|
|
void bsrl(CpuRegister dst, CpuRegister src);
|
|
void bsrl(CpuRegister dst, const Address& src);
|
|
void bsrq(CpuRegister dst, CpuRegister src);
|
|
void bsrq(CpuRegister dst, const Address& src);
|
|
|
|
void popcntl(CpuRegister dst, CpuRegister src);
|
|
void popcntl(CpuRegister dst, const Address& src);
|
|
void popcntq(CpuRegister dst, CpuRegister src);
|
|
void popcntq(CpuRegister dst, const Address& src);
|
|
|
|
void rorl(CpuRegister reg, const Immediate& imm);
|
|
void rorl(CpuRegister operand, CpuRegister shifter);
|
|
void roll(CpuRegister reg, const Immediate& imm);
|
|
void roll(CpuRegister operand, CpuRegister shifter);
|
|
|
|
void rorq(CpuRegister reg, const Immediate& imm);
|
|
void rorq(CpuRegister operand, CpuRegister shifter);
|
|
void rolq(CpuRegister reg, const Immediate& imm);
|
|
void rolq(CpuRegister operand, CpuRegister shifter);
|
|
|
|
void repne_scasb();
|
|
void repne_scasw();
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void repe_cmpsw();
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void repe_cmpsl();
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void repe_cmpsq();
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|
void rep_movsw();
|
|
|
|
//
|
|
// Macros for High-level operations.
|
|
//
|
|
|
|
void AddImmediate(CpuRegister reg, const Immediate& imm);
|
|
|
|
void LoadDoubleConstant(XmmRegister dst, double value);
|
|
|
|
void LockCmpxchgl(const Address& address, CpuRegister reg) {
|
|
lock()->cmpxchgl(address, reg);
|
|
}
|
|
|
|
void LockCmpxchgq(const Address& address, CpuRegister reg) {
|
|
lock()->cmpxchgq(address, reg);
|
|
}
|
|
|
|
//
|
|
// Misc. functionality
|
|
//
|
|
int PreferredLoopAlignment() { return 16; }
|
|
void Align(int alignment, int offset);
|
|
void Bind(Label* label) override;
|
|
void Jump(Label* label) override {
|
|
jmp(label);
|
|
}
|
|
void Bind(NearLabel* label);
|
|
|
|
// Add a double to the constant area, returning the offset into
|
|
// the constant area where the literal resides.
|
|
size_t AddDouble(double v) { return constant_area_.AddDouble(v); }
|
|
|
|
// Add a float to the constant area, returning the offset into
|
|
// the constant area where the literal resides.
|
|
size_t AddFloat(float v) { return constant_area_.AddFloat(v); }
|
|
|
|
// Add an int32_t to the constant area, returning the offset into
|
|
// the constant area where the literal resides.
|
|
size_t AddInt32(int32_t v) {
|
|
return constant_area_.AddInt32(v);
|
|
}
|
|
|
|
// Add an int32_t to the end of the constant area, returning the offset into
|
|
// the constant area where the literal resides.
|
|
size_t AppendInt32(int32_t v) {
|
|
return constant_area_.AppendInt32(v);
|
|
}
|
|
|
|
// Add an int64_t to the constant area, returning the offset into
|
|
// the constant area where the literal resides.
|
|
size_t AddInt64(int64_t v) { return constant_area_.AddInt64(v); }
|
|
|
|
// Add the contents of the constant area to the assembler buffer.
|
|
void AddConstantArea();
|
|
|
|
// Is the constant area empty? Return true if there are no literals in the constant area.
|
|
bool IsConstantAreaEmpty() const { return constant_area_.GetSize() == 0; }
|
|
|
|
// Return the current size of the constant area.
|
|
size_t ConstantAreaSize() const { return constant_area_.GetSize(); }
|
|
|
|
//
|
|
// Heap poisoning.
|
|
//
|
|
|
|
// Poison a heap reference contained in `reg`.
|
|
void PoisonHeapReference(CpuRegister reg) { negl(reg); }
|
|
// Unpoison a heap reference contained in `reg`.
|
|
void UnpoisonHeapReference(CpuRegister reg) { negl(reg); }
|
|
// Poison a heap reference contained in `reg` if heap poisoning is enabled.
|
|
void MaybePoisonHeapReference(CpuRegister reg) {
|
|
if (kPoisonHeapReferences) {
|
|
PoisonHeapReference(reg);
|
|
}
|
|
}
|
|
// Unpoison a heap reference contained in `reg` if heap poisoning is enabled.
|
|
void MaybeUnpoisonHeapReference(CpuRegister reg) {
|
|
if (kPoisonHeapReferences) {
|
|
UnpoisonHeapReference(reg);
|
|
}
|
|
}
|
|
|
|
bool CpuHasAVXorAVX2FeatureFlag();
|
|
|
|
private:
|
|
void EmitUint8(uint8_t value);
|
|
void EmitInt32(int32_t value);
|
|
void EmitInt64(int64_t value);
|
|
void EmitRegisterOperand(uint8_t rm, uint8_t reg);
|
|
void EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg);
|
|
void EmitFixup(AssemblerFixup* fixup);
|
|
void EmitOperandSizeOverride();
|
|
|
|
void EmitOperand(uint8_t rm, const Operand& operand);
|
|
void EmitImmediate(const Immediate& imm, bool is_16_op = false);
|
|
void EmitComplex(
|
|
uint8_t rm, const Operand& operand, const Immediate& immediate, bool is_16_op = false);
|
|
void EmitLabel(Label* label, int instruction_size);
|
|
void EmitLabelLink(Label* label);
|
|
void EmitLabelLink(NearLabel* label);
|
|
|
|
void EmitGenericShift(bool wide, int rm, CpuRegister reg, const Immediate& imm);
|
|
void EmitGenericShift(bool wide, int rm, CpuRegister operand, CpuRegister shifter);
|
|
|
|
// If any input is not false, output the necessary rex prefix.
|
|
void EmitOptionalRex(bool force, bool w, bool r, bool x, bool b);
|
|
|
|
// Emit a rex prefix byte if necessary for reg. ie if reg is a register in the range R8 to R15.
|
|
void EmitOptionalRex32(CpuRegister reg);
|
|
void EmitOptionalRex32(CpuRegister dst, CpuRegister src);
|
|
void EmitOptionalRex32(XmmRegister dst, XmmRegister src);
|
|
void EmitOptionalRex32(CpuRegister dst, XmmRegister src);
|
|
void EmitOptionalRex32(XmmRegister dst, CpuRegister src);
|
|
void EmitOptionalRex32(const Operand& operand);
|
|
void EmitOptionalRex32(CpuRegister dst, const Operand& operand);
|
|
void EmitOptionalRex32(XmmRegister dst, const Operand& operand);
|
|
|
|
// Emit a REX.W prefix plus necessary register bit encodings.
|
|
void EmitRex64();
|
|
void EmitRex64(CpuRegister reg);
|
|
void EmitRex64(const Operand& operand);
|
|
void EmitRex64(CpuRegister dst, CpuRegister src);
|
|
void EmitRex64(CpuRegister dst, const Operand& operand);
|
|
void EmitRex64(XmmRegister dst, const Operand& operand);
|
|
void EmitRex64(XmmRegister dst, CpuRegister src);
|
|
void EmitRex64(CpuRegister dst, XmmRegister src);
|
|
|
|
// Emit a REX prefix to normalize byte registers plus necessary register bit encodings.
|
|
void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src);
|
|
void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand);
|
|
|
|
uint8_t EmitVexPrefixByteZero(bool is_twobyte_form);
|
|
uint8_t EmitVexPrefixByteOne(bool R, bool X, bool B, int SET_VEX_M);
|
|
uint8_t EmitVexPrefixByteOne(bool R,
|
|
X86_64ManagedRegister operand,
|
|
int SET_VEX_L,
|
|
int SET_VEX_PP);
|
|
uint8_t EmitVexPrefixByteTwo(bool W,
|
|
X86_64ManagedRegister operand,
|
|
int SET_VEX_L,
|
|
int SET_VEX_PP);
|
|
uint8_t EmitVexPrefixByteTwo(bool W,
|
|
int SET_VEX_L,
|
|
int SET_VEX_PP);
|
|
ConstantArea constant_area_;
|
|
bool has_AVX_; // x86 256bit SIMD AVX.
|
|
bool has_AVX2_; // x86 256bit SIMD AVX 2.0.
|
|
|
|
DISALLOW_COPY_AND_ASSIGN(X86_64Assembler);
|
|
};
|
|
|
|
inline void X86_64Assembler::EmitUint8(uint8_t value) {
|
|
buffer_.Emit<uint8_t>(value);
|
|
}
|
|
|
|
inline void X86_64Assembler::EmitInt32(int32_t value) {
|
|
buffer_.Emit<int32_t>(value);
|
|
}
|
|
|
|
inline void X86_64Assembler::EmitInt64(int64_t value) {
|
|
// Write this 64-bit value as two 32-bit words for alignment reasons
|
|
// (this is essentially when running on ARM, which does not allow
|
|
// 64-bit unaligned accesses). We assume little-endianness here.
|
|
EmitInt32(Low32Bits(value));
|
|
EmitInt32(High32Bits(value));
|
|
}
|
|
|
|
inline void X86_64Assembler::EmitRegisterOperand(uint8_t rm, uint8_t reg) {
|
|
CHECK_GE(rm, 0);
|
|
CHECK_LT(rm, 8);
|
|
buffer_.Emit<uint8_t>((0xC0 | (reg & 7)) + (rm << 3));
|
|
}
|
|
|
|
inline void X86_64Assembler::EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) {
|
|
EmitRegisterOperand(rm, static_cast<uint8_t>(reg.AsFloatRegister()));
|
|
}
|
|
|
|
inline void X86_64Assembler::EmitFixup(AssemblerFixup* fixup) {
|
|
buffer_.EmitFixup(fixup);
|
|
}
|
|
|
|
inline void X86_64Assembler::EmitOperandSizeOverride() {
|
|
EmitUint8(0x66);
|
|
}
|
|
|
|
} // namespace x86_64
|
|
} // namespace art
|
|
|
|
#endif // ART_COMPILER_UTILS_X86_64_ASSEMBLER_X86_64_H_
|