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210 lines
6.2 KiB
210 lines
6.2 KiB
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Chris Wilson <chris@chris-wilson.co.uk>
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*
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*/
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#include "igt.h"
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#include <unistd.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/ioctl.h>
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#include <sys/time.h>
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#include "drm.h"
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IGT_TEST_DESCRIPTION("Simulates SNA behaviour using negative self-relocations"
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" for STATE_BASE_ADDRESS command packets.");
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#define USE_LUT (1 << 12)
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#define BIAS (256*1024)
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/* Simulates SNA behaviour using negative self-relocations for
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* STATE_BASE_ADDRESS command packets. If they wrap around (to values greater
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* than the total size of the GTT), the GPU will hang.
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* See https://bugs.freedesktop.org/show_bug.cgi?id=78533
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*/
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static void negative_reloc(int fd, unsigned engine, unsigned flags)
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{
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_exec_object2 obj;
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struct drm_i915_gem_relocation_entry reloc[1000];
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uint64_t gtt_max = gem_aperture_size(fd);
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uint32_t bbe = MI_BATCH_BUFFER_END;
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uint64_t *offsets;
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int i;
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gem_require_ring(fd, engine);
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igt_require(intel_gen(intel_get_drm_devid(fd)) >= 7);
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memset(&obj, 0, sizeof(obj));
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obj.handle = gem_create(fd, 8192);
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gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = (uintptr_t)&obj;
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execbuf.buffer_count = 1;
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execbuf.flags = engine | (flags & USE_LUT);
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igt_require(__gem_execbuf(fd, &execbuf) == 0);
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igt_info("Found offset %lld for 4k batch\n", (long long)obj.offset);
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/*
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* Ideally we'd like to be able to control where the kernel is going to
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* place the buffer. We don't SKIP here because it causes the test
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* to "randomly" flip-flop between the SKIP and PASS states.
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*/
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if (obj.offset < BIAS) {
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igt_info("Offset is below BIAS, not testing anything\n");
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return;
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}
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memset(reloc, 0, sizeof(reloc));
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for (i = 0; i < ARRAY_SIZE(reloc); i++) {
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reloc[i].offset = 8 + 8*i;
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reloc[i].delta = -BIAS*i/1024;
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reloc[i].presumed_offset = -1;
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reloc[i].target_handle = flags & USE_LUT ? 0 : obj.handle;
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reloc[i].read_domains = I915_GEM_DOMAIN_COMMAND;
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}
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obj.relocation_count = i;
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obj.relocs_ptr = (uintptr_t)reloc;
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gem_execbuf(fd, &execbuf);
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igt_info("Batch is now at offset %#llx, max GTT %#llx\n",
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(long long)obj.offset, (long long)gtt_max);
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offsets = gem_mmap__cpu(fd, obj.handle, 0, 8192, PROT_READ);
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gem_set_domain(fd, obj.handle, I915_GEM_DOMAIN_CPU, 0);
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gem_close(fd, obj.handle);
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for (i = 0; i < ARRAY_SIZE(reloc); i++)
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igt_assert_f(offsets[1 + i] < gtt_max,
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"Offset[%d]=%#llx, expected less than %#llx\n",
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i, (long long)offsets[i+i], (long long)gtt_max);
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munmap(offsets, 8192);
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}
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static void negative_reloc_blt(int fd)
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{
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const int gen = intel_gen(intel_get_drm_devid(fd));
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_exec_object2 obj[1024][2];
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struct drm_i915_gem_relocation_entry reloc;
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uint32_t buf[1024], *b;
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int i;
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memset(&reloc, 0, sizeof(reloc));
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reloc.offset = 4 * sizeof(uint32_t);
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reloc.presumed_offset = ~0ULL;
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reloc.delta = -4096;
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reloc.target_handle = 0;
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reloc.read_domains = I915_GEM_DOMAIN_RENDER;
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reloc.write_domain = I915_GEM_DOMAIN_RENDER;
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for (i = 0; i < 1024; i++) {
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memset(obj[i], 0, sizeof(obj[i]));
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obj[i][0].handle = gem_create(fd, 4096);
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obj[i][0].flags = EXEC_OBJECT_NEEDS_FENCE;
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b = buf;
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*b++ = XY_COLOR_BLT_CMD_NOLEN |
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((gen >= 8) ? 5 : 4) |
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COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB;
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*b++ = 0xf0 << 16 | 1 << 25 | 1 << 24 | 4096;
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*b++ = 1 << 16 | 0;
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*b++ = 2 << 16 | 1024;
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*b++ = ~0;
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if (gen >= 8)
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*b++ = ~0;
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*b++ = 0xc0ffee ^ i;
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*b++ = MI_BATCH_BUFFER_END;
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if ((b - buf) & 1)
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*b++ = 0;
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obj[i][1].handle = gem_create(fd, 4096);
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gem_write(fd, obj[i][1].handle, 0, buf, (b - buf) * sizeof(uint32_t));
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obj[i][1].relocation_count = 1;
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obj[i][1].relocs_ptr = (uintptr_t)&reloc;
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}
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffer_count = 2;
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execbuf.batch_len = (b - buf) * sizeof(uint32_t);
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execbuf.flags = USE_LUT;
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if (gen >= 6)
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execbuf.flags |= I915_EXEC_BLT;
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for (i = 0; i < 1024; i++) {
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execbuf.buffers_ptr = (uintptr_t)obj[i];
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gem_execbuf(fd, &execbuf);
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}
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for (i = 1024; i--;) {
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gem_read(fd, obj[i][0].handle,
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i*sizeof(uint32_t), buf + i, sizeof(uint32_t));
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gem_close(fd, obj[i][0].handle);
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gem_close(fd, obj[i][1].handle);
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}
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if (0) {
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for (i = 0; i < 1024; i += 8)
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igt_info("%08x %08x %08x %08x %08x %08x %08x %08x\n",
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buf[i + 0], buf[i + 1], buf[i + 2], buf[i + 3],
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buf[i + 4], buf[i + 5], buf[i + 6], buf[i + 7]);
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}
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for (i = 0; i < 1024; i++)
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igt_assert_eq(buf[i], 0xc0ffee ^ i);
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}
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igt_main
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{
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const struct intel_execution_engine *e;
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int fd = -1;
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igt_fixture {
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fd = drm_open_driver(DRIVER_INTEL);
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igt_require_gem(fd);
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}
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for (e = intel_execution_engines; e->name; e++) {
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igt_subtest_f("negative-reloc-%s", e->name)
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negative_reloc(fd, e->exec_id | e->flags, 0);
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igt_subtest_f("negative-reloc-lut-%s", e->name)
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negative_reloc(fd, e->exec_id | e->flags, USE_LUT);
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}
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igt_subtest("negative-reloc-bltcopy")
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negative_reloc_blt(fd);
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igt_fixture
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close(fd);
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}
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