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310 lines
8.1 KiB
310 lines
8.1 KiB
/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Chris Wilson <chris@chris-wilson.co.uk>
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*
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*/
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/*
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* Testcase: Test the relocations through the CPU domain
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*
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* Attempt to stress test performing relocations whilst the batch is in the
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* CPU domain.
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*
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* A freshly allocated buffer starts in the CPU domain, and the pwrite
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* should also be performed whilst in the CPU domain and so we should
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* execute the relocations within the CPU domain. If for any reason one of
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* those steps should land it in the GTT domain, we take the secondary
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* precaution of filling the mappable portion of the GATT.
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*
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* In order to detect whether a relocation fails, we first fill a target
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* buffer with a sequence of invalid commands that would cause the GPU to
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* immediate hang, and then attempt to overwrite them with a legal, if
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* short, batchbuffer using a BLT. Then we come to execute the bo, if the
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* relocation fail and we either copy across all zeros or garbage, then the
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* GPU will hang.
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*/
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#include "igt.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/time.h>
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#include <drm.h>
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#include "intel_bufmgr.h"
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#define MI_INSTR(opcode, flags) ((opcode) << 23 | (flags))
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IGT_TEST_DESCRIPTION("Test the relocations through the CPU domain.");
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static uint32_t *
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gen2_emit_store_addr(uint32_t *cs, struct drm_i915_gem_relocation_entry *addr)
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{
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*cs++ = MI_STORE_DWORD_IMM - 1;
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addr->offset += sizeof(*cs);
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cs += 1; /* addr */
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cs += 1; /* value: implicit 0xffffffff */
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return cs;
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}
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static uint32_t *
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gen4_emit_store_addr(uint32_t *cs, struct drm_i915_gem_relocation_entry *addr)
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{
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*cs++ = MI_STORE_DWORD_IMM;
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*cs++ = 0;
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addr->offset += 2 * sizeof(*cs);
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cs += 1; /* addr */
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cs += 1; /* value: implicit 0xffffffff */
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return cs;
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}
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static uint32_t *
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gen8_emit_store_addr(uint32_t *cs, struct drm_i915_gem_relocation_entry *addr)
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{
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*cs++ = (MI_STORE_DWORD_IMM | 1 << 21) + 1;
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addr->offset += sizeof(*cs);
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igt_assert((addr->delta & 7) == 0);
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cs += 2; /* addr */
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cs += 2; /* value: implicit 0xffffffffffffffff */
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return cs;
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}
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static uint32_t *
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gen2_emit_bb_start(uint32_t *cs, struct drm_i915_gem_relocation_entry *addr)
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{
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*cs++ = MI_BATCH_BUFFER_START | 2 << 6;
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addr->offset += sizeof(*cs);
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addr->delta += 1;
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cs += 1; /* addr */
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return cs;
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}
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static uint32_t *
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gen4_emit_bb_start(uint32_t *cs, struct drm_i915_gem_relocation_entry *addr)
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{
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*cs++ = MI_BATCH_BUFFER_START | 2 << 6 | 1 << 8;
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addr->offset += sizeof(*cs);
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cs += 1; /* addr */
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return cs;
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}
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static uint32_t *
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gen6_emit_bb_start(uint32_t *cs, struct drm_i915_gem_relocation_entry *addr)
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{
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*cs++ = MI_BATCH_BUFFER_START | 1 << 8;
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addr->offset += sizeof(*cs);
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cs += 1; /* addr */
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return cs;
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}
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static uint32_t *
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hsw_emit_bb_start(uint32_t *cs, struct drm_i915_gem_relocation_entry *addr)
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{
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*cs++ = MI_BATCH_BUFFER_START | 2 << 6 | 1 << 8 | 1 << 13;
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addr->offset += sizeof(*cs);
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cs += 1; /* addr */
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return cs;
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}
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static uint32_t *
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gen8_emit_bb_start(uint32_t *cs, struct drm_i915_gem_relocation_entry *addr)
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{
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if (((uintptr_t)cs & 7) == 0) {
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*cs++ = MI_NOOP; /* align addr for MI_STORE_DWORD_IMM */
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addr->offset += sizeof(*cs);
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}
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*cs++ = MI_BATCH_BUFFER_START + 1;
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addr->offset += sizeof(*cs);
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cs += 2; /* addr */
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return cs;
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}
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static void *
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create_tmpl(int i915, struct drm_i915_gem_relocation_entry *reloc)
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{
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const uint32_t devid = intel_get_drm_devid(i915);
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const int gen = intel_gen(devid);
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uint32_t *(*emit_store_addr)(uint32_t *cs,
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struct drm_i915_gem_relocation_entry *addr);
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uint32_t *(*emit_bb_start)(uint32_t *cs,
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struct drm_i915_gem_relocation_entry *reloc);
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void *tmpl;
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if (gen >= 8)
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emit_store_addr = gen8_emit_store_addr;
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else if (gen >= 4)
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emit_store_addr = gen4_emit_store_addr;
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else
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emit_store_addr = gen2_emit_store_addr;
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if (gen >= 8)
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emit_bb_start = gen8_emit_bb_start;
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else if (IS_HASWELL(devid))
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emit_bb_start = hsw_emit_bb_start;
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else if (gen >= 6)
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emit_bb_start = gen6_emit_bb_start;
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else if (gen >= 4)
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emit_bb_start = gen4_emit_bb_start;
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else
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emit_bb_start = gen2_emit_bb_start;
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tmpl = malloc(4096);
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igt_assert(tmpl);
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memset(tmpl, 0xff, 4096);
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/* Jump over the booby traps to the end */
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reloc[0].delta = 64;
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emit_bb_start(tmpl, &reloc[0]);
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/* Restore the bad address to catch missing relocs */
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reloc[1].offset = 64;
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reloc[1].delta = reloc[0].offset;
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*emit_store_addr(tmpl + 64, &reloc[1]) = MI_BATCH_BUFFER_END;
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return tmpl;
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}
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static void run_test(int i915, int count)
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{
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_relocation_entry reloc[2];
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struct drm_i915_gem_exec_object2 obj;
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uint32_t *handles;
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uint32_t *tmpl;
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handles = malloc(count * sizeof(uint32_t));
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igt_assert(handles);
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memset(reloc, 0, sizeof(reloc));
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tmpl = create_tmpl(i915, reloc);
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for (int i = 0; i < count; i++) {
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handles[i] = gem_create(i915, 4096);
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gem_write(i915, handles[i], 0, tmpl, 4096);
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}
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free(tmpl);
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memset(&obj, 0, sizeof(obj));
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obj.relocs_ptr = to_user_pointer(reloc);
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obj.relocation_count = ARRAY_SIZE(reloc);
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffers_ptr = to_user_pointer(&obj);
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execbuf.buffer_count = 1;
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/* fill the entire gart with batches and run them */
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for (int i = 0; i < count; i++) {
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obj.handle = handles[i];
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reloc[0].target_handle = obj.handle;
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reloc[0].presumed_offset = -1;
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reloc[1].target_handle = obj.handle;
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reloc[1].presumed_offset = -1;
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gem_execbuf(i915, &execbuf);
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}
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/* And again in reverse to try and catch the relocation code out */
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for (int i = 0; i < count; i++) {
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obj.handle = handles[count - i - 1];
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reloc[0].target_handle = obj.handle;
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reloc[0].presumed_offset = -1;
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reloc[1].target_handle = obj.handle;
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reloc[1].presumed_offset = -1;
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gem_execbuf(i915, &execbuf);
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}
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/* Third time unlucky? */
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for (int i = 0; i < count; i++) {
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obj.handle = handles[i];
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reloc[0].target_handle = obj.handle;
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reloc[0].presumed_offset = -1;
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reloc[1].target_handle = obj.handle;
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reloc[1].presumed_offset = -1;
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gem_set_domain(i915, obj.handle,
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I915_GEM_DOMAIN_CPU,
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I915_GEM_DOMAIN_CPU);
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gem_execbuf(i915, &execbuf);
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}
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for (int i = 0; i < count; i++)
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gem_close(i915, handles[i]);
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free(handles);
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}
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igt_main
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{
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int i915;
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igt_fixture {
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i915 = drm_open_driver(DRIVER_INTEL);
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igt_require_gem(i915);
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/* could use BLT_FILL instead for gen2 */
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igt_require(gem_can_store_dword(i915, 0));
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igt_fork_hang_detector(i915);
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}
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igt_subtest("basic")
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run_test(i915, 1);
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igt_subtest("full") {
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uint64_t aper_size = gem_mappable_aperture_size();
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unsigned long count = aper_size / 4096 + 1;
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intel_require_memory(count, 4096, CHECK_RAM);
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run_test(i915, count);
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}
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igt_subtest("forked") {
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uint64_t aper_size = gem_mappable_aperture_size();
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unsigned long count = aper_size / 4096 + 1;
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int ncpus = sysconf(_SC_NPROCESSORS_ONLN);
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intel_require_memory(count, 4096, CHECK_RAM);
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igt_fork(child, ncpus)
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run_test(i915, count / ncpus + 1);
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igt_waitchildren();
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}
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igt_fixture {
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igt_stop_hang_detector();
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}
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}
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