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125 lines
3.5 KiB
125 lines
3.5 KiB
/*
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* Copyright © 2011 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Daniel Vetter <daniel.vetter@ffwll.ch> (based on gem_storedw_*.c)
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*
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*/
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#include "igt.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <fcntl.h>
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#include <inttypes.h>
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/time.h>
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#include "drm.h"
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#include "intel_bufmgr.h"
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#include "i830_reg.h"
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static drm_intel_bufmgr *bufmgr;
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struct intel_batchbuffer *batch;
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static drm_intel_bo *target_buffer, *blt_bo;
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/*
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* Testcase: Basic check for missed irqs on blt
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*
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* Execs one large and then immediately a tiny batch on the blt ring. Then waits
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* on the second batch. This hopefully catches races in our irq acknowledgement.
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*/
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IGT_TEST_DESCRIPTION("Basic check for missed IRQs on blt ring.");
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#define MI_COND_BATCH_BUFFER_END (0x36<<23 | 1)
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#define MI_DO_COMPARE (1<<21)
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static void
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dummy_reloc_loop(void)
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{
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int i;
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for (i = 0; i < 0x800; i++) {
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BLIT_COPY_BATCH_START(0);
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OUT_BATCH((3 << 24) | /* 32 bits */
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(0xcc << 16) | /* copy ROP */
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4*4096);
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OUT_BATCH(2048 << 16 | 0);
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OUT_BATCH((4096) << 16 | (2048));
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OUT_RELOC_FENCED(blt_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH(0 << 16 | 0);
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OUT_BATCH(4*4096);
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OUT_RELOC_FENCED(blt_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
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ADVANCE_BATCH();
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intel_batchbuffer_flush(batch);
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BEGIN_BATCH(4, 1);
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OUT_BATCH(MI_FLUSH_DW | 1);
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OUT_BATCH(0); /* reserved */
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OUT_RELOC(target_buffer, I915_GEM_DOMAIN_RENDER,
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I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH(MI_NOOP | (1<<22) | (0xf));
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ADVANCE_BATCH();
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intel_batchbuffer_flush(batch);
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drm_intel_bo_map(target_buffer, 0);
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// map to force completion
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drm_intel_bo_unmap(target_buffer);
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}
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}
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igt_simple_main
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{
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int fd;
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int devid;
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igt_skip_on_simulation();
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fd = drm_open_driver(DRIVER_INTEL);
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igt_require_gem(fd);
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devid = intel_get_drm_devid(fd);
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igt_require_f(HAS_BLT_RING(devid),
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"not (yet) implemented for pre-snb\n");
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bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
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igt_assert(bufmgr);
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drm_intel_bufmgr_gem_enable_reuse(bufmgr);
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batch = intel_batchbuffer_alloc(bufmgr, devid);
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igt_assert(batch);
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target_buffer = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
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igt_assert(target_buffer);
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blt_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4*4096*4096, 4096);
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igt_assert(blt_bo);
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dummy_reloc_loop();
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drm_intel_bo_unreference(target_buffer);
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intel_batchbuffer_free(batch);
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drm_intel_bufmgr_destroy(bufmgr);
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close(fd);
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}
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