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237 lines
6.6 KiB
237 lines
6.6 KiB
/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "igt.h"
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#include "igt_rand.h"
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IGT_TEST_DESCRIPTION("Fill the GTT with batches.");
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#define BATCH_SIZE (4096<<10)
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struct batch {
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uint32_t handle;
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void *ptr;
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};
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static void xchg_batch(void *array, unsigned int i, unsigned int j)
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{
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struct batch *batches = array;
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struct batch tmp;
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tmp = batches[i];
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batches[i] = batches[j];
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batches[j] = tmp;
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}
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static void submit(int fd, int gen,
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struct drm_i915_gem_execbuffer2 *eb,
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struct drm_i915_gem_relocation_entry *reloc,
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struct batch *batches, unsigned int count)
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{
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struct drm_i915_gem_exec_object2 obj;
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uint32_t batch[16];
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unsigned n;
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memset(&obj, 0, sizeof(obj));
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obj.relocs_ptr = to_user_pointer(reloc);
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obj.relocation_count = 2;
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memset(reloc, 0, 2*sizeof(*reloc));
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reloc[0].offset = eb->batch_start_offset;
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reloc[0].offset += sizeof(uint32_t);
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reloc[0].delta = BATCH_SIZE - eb->batch_start_offset - 8;
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reloc[0].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
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reloc[1].offset = eb->batch_start_offset;
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reloc[1].offset += 3*sizeof(uint32_t);
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reloc[1].read_domains = I915_GEM_DOMAIN_INSTRUCTION;
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n = 0;
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batch[n] = MI_STORE_DWORD_IMM | (gen < 6 ? 1 << 22 : 0);
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if (gen >= 8) {
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batch[n] |= 1 << 21;
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batch[n]++;
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batch[++n] = reloc[0].delta;/* lower_32_bits(address) */
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batch[++n] = 0; /* upper_32_bits(address) */
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} else if (gen >= 4) {
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batch[++n] = 0;
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batch[++n] = reloc[0].delta;/* lower_32_bits(address) */
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reloc[0].offset += sizeof(uint32_t);
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} else {
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batch[n]--;
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batch[++n] = reloc[0].delta;/* lower_32_bits(address) */
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reloc[1].offset -= sizeof(uint32_t);
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}
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batch[++n] = 0; /* lower_32_bits(value) */
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batch[++n] = 0; /* upper_32_bits(value) / nop */
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batch[++n] = MI_BATCH_BUFFER_END;
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eb->buffers_ptr = to_user_pointer(&obj);
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for (unsigned i = 0; i < count; i++) {
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obj.handle = batches[i].handle;
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reloc[0].target_handle = obj.handle;
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reloc[1].target_handle = obj.handle;
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obj.offset = 0;
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reloc[0].presumed_offset = obj.offset;
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reloc[1].presumed_offset = obj.offset;
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memcpy(batches[i].ptr + eb->batch_start_offset,
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batch, sizeof(batch));
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gem_execbuf(fd, eb);
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}
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/* As we have been lying about the write_domain, we need to do a sync */
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gem_sync(fd, obj.handle);
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}
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static void fillgtt(int fd, unsigned ring, int timeout)
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{
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const int gen = intel_gen(intel_get_drm_devid(fd));
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struct drm_i915_gem_execbuffer2 execbuf;
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struct drm_i915_gem_relocation_entry reloc[2];
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volatile uint64_t *shared;
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struct batch *batches;
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unsigned engines[16];
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unsigned nengine;
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unsigned engine;
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uint64_t size;
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unsigned count;
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shared = mmap(NULL, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
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igt_assert(shared != MAP_FAILED);
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nengine = 0;
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if (ring == 0) {
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for_each_physical_engine(fd, engine) {
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if (!gem_can_store_dword(fd, engine))
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continue;
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engines[nengine++] = engine;
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}
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} else {
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gem_require_ring(fd, ring);
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igt_require(gem_can_store_dword(fd, ring));
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engines[nengine++] = ring;
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}
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igt_require(nengine);
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size = gem_aperture_size(fd);
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if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */
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size = 1ull << 32;
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igt_require(size < (1ull<<32) * BATCH_SIZE);
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count = size / BATCH_SIZE + 1;
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igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n",
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count, (long long)size, nengine);
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intel_require_memory(count, BATCH_SIZE, CHECK_RAM);
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intel_detect_and_clear_missed_interrupts(fd);
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memset(&execbuf, 0, sizeof(execbuf));
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execbuf.buffer_count = 1;
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if (gen < 6)
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execbuf.flags |= I915_EXEC_SECURE;
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batches = calloc(count, sizeof(*batches));
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igt_assert(batches);
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for (unsigned i = 0; i < count; i++) {
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batches[i].handle = gem_create(fd, BATCH_SIZE);
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batches[i].ptr =
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__gem_mmap__wc(fd, batches[i].handle,
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0, BATCH_SIZE, PROT_WRITE);
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if (!batches[i].ptr) {
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batches[i].ptr =
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__gem_mmap__gtt(fd, batches[i].handle,
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BATCH_SIZE, PROT_WRITE);
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}
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igt_require(batches[i].ptr);
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}
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/* Flush all memory before we start the timer */
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submit(fd, gen, &execbuf, reloc, batches, count);
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igt_fork(child, nengine) {
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uint64_t cycles = 0;
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hars_petruska_f54_1_random_perturb(child);
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igt_permute_array(batches, count, xchg_batch);
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execbuf.batch_start_offset = child*64;
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execbuf.flags |= engines[child];
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igt_until_timeout(timeout) {
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submit(fd, gen, &execbuf, reloc, batches, count);
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for (unsigned i = 0; i < count; i++) {
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uint64_t offset, delta;
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offset = *(uint64_t *)(batches[i].ptr + reloc[1].offset);
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delta = *(uint64_t *)(batches[i].ptr + reloc[0].delta);
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igt_assert_eq_u64(offset, delta);
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}
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cycles++;
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}
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shared[child] = cycles;
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igt_info("engine[%d]: %llu cycles\n", child, (long long)cycles);
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}
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igt_waitchildren();
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for (unsigned i = 0; i < count; i++) {
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munmap(batches[i].ptr, BATCH_SIZE);
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gem_close(fd, batches[i].handle);
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}
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shared[nengine] = 0;
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for (unsigned i = 0; i < nengine; i++)
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shared[nengine] += shared[i];
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igt_info("Total: %llu cycles\n", (long long)shared[nengine]);
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igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
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}
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igt_main
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{
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const struct intel_execution_engine *e;
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int device = -1;
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igt_skip_on_simulation();
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igt_fixture {
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device = drm_open_driver(DRIVER_INTEL);
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igt_require_gem(device);
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igt_require(gem_can_store_dword(device, 0));
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igt_fork_hang_detector(device);
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}
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igt_subtest("basic")
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fillgtt(device, 0, 1); /* just enough to run a single pass */
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for (e = intel_execution_engines; e->name; e++)
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igt_subtest_f("%s", e->name)
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fillgtt(device, e->exec_id | e->flags, 20);
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igt_subtest("all")
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fillgtt(device, 0, 150);
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igt_fixture {
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igt_stop_hang_detector();
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close(device);
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}
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}
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